DS90UB928Q-Q1 Datasheet, PDF (57/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

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Typical Application (continued)
FPD-Link
VDDIO VDD33
(1.8V or 3.3V) (3.3V)
DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
FPD-Link
(OpenLDI)
VDD33 VDDIO
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RxIN3+/-
RxIN2+/-
RxIN1+/-
RxIN0+/-
RxCLKIN+/-
PDB
I2S AUDIO ⁶
(Surround)
SCL
SDA
IDx
DOUT+
DOUT-
DS90UB927Q
Serializer
FPD-Link III
1 Pair/AC Coupled
100Q STP Cable
CMF
CMF
OEN
OSS_SEL
PDB
MAPSEL
LFMODE
REPEAT
MAPSEL
LFMODE
REPEAT
BACKWD
BISTEN
MODE_SEL
RIN+
RIN-
DS90UB928Q
Deserializer
TxOUT3+/-
TxOUT2+/-
TxOUT1+/-
TxOUT0+/-
TxCLKOUT+/-
LOCK
PASS
6
I2S AUDIO
(Surround)
MCLK
SCL
SDA
IDx
LVDS Display
720p or
Graphic
Processor
Figure 42. Typical Display System Diagram
9.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 9. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for RIN±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
100 nF
78 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Transmission Media
The DS90UB927Q-Q1 and DS90UB928Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer must
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, and so forth.) and the
application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width (E_W) and eye opening height (E_H). A differential probe should be used to
measure across the termination resistor of 100 Ω between the CMLOUTP and CMLOUTN pins.
9.2.2.2 Display Application
The DS90UB928Q-Q1, in conjunction with the DS90UB925Q-Q1 or DS90UB927Q-Q1, is intended for interfacing
with a host (graphics processor) and a display supporting 24-bit color depth (RGB888) and high-definition (720p)
digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three
control bits (VS, HS, and DE) and four I2S audio streams.
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