DS90UB928Q-Q1 Datasheet, PDF (2/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Application Diagram .............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 4
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ..................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information .................................................. 8
7.5 DC Electrical Characteristics .................................... 9
7.6 AC Electrical Characteristics................................... 11
7.7 Timing Requirements for the Serial Control Bus .... 12
7.8 Timing Requirements .............................................. 12
7.9 DC and AC Serial Control Bus Characteristics....... 13
7.10 Typical Characteristics .......................................... 17
8 Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 31
8.5 Programming........................................................... 38
8.6 Register Maps ......................................................... 39
9 Application and Implementation ........................ 55
9.1 Application Information............................................ 55
9.2 Typical Application .................................................. 55
9.3 AV Mute Prevention ................................................ 58
9.4 OEN Toggling Limitation ......................................... 58
10 Power Supply Recommendations ..................... 58
10.1 Power Up Requirements and PDB Pin ................. 58
11 Layout................................................................... 60
11.1 Layout Guidelines ................................................. 60
11.2 Layout Example .................................................... 61
12 Device and Documentation Support ................. 63
12.1 Documentation Support ........................................ 63
12.2 Receiving Notification of Documentation Updates 63
12.3 Community Resources.......................................... 63
12.4 Trademarks ........................................................... 63
12.5 Electrostatic Discharge Caution ............................ 63
12.6 Glossary ................................................................ 63
13 Mechanical, Packaging, and Orderable
Information ........................................................... 63
5 Revision History
Changes from Revision B (January 2015) to Revision C
Page
• Added "OpenLDI". ................................................................................................................................................................. 1
• Added AV Mute Prevention section. ...................................................................................................................................... 2
• Added OEN Toggling Limitation. ........................................................................................................................................... 2
• Changed the shared function. ............................................................................................................................................... 4
• Added the shared function ..................................................................................................................................................... 5
• Changed Pin name .............................................................................................................................................................. 11
• Added Input Jitter specification. ........................................................................................................................................... 11
• Added I2S Set-up Time. ...................................................................................................................................................... 12
• Added I2S Hold Time. ......................................................................................................................................................... 12
• Added Read Register at the first step. ................................................................................................................................ 26
• Changed the updated GPIO Configuration table. ................................................................................................................ 27
• Changed to one tenth of Resistor value ............................................................................................................................... 33
• Changed and swapped IDEAL RATIO and IDEAL VR2 values. .......................................................................................... 38
• Changed to one tenth of Resistor value ............................................................................................................................... 38
• Changed and Revised data to 0x01 ..................................................................................................................................... 45
• Changed and revised GPIO Direction description. .............................................................................................................. 47
• Changed and revised Register Type to RW from R. ........................................................................................................... 48
• Added and disclosed Link Error Count Register. ................................................................................................................ 51
• Added and disclosed LVDS Setting Register. ..................................................................................................................... 52
• Changed and revised Register Address. ............................................................................................................................. 54
• Added AV Mute Prevention section. .................................................................................................................................... 58
• Added OEN Toggling Limitation. ......................................................................................................................................... 58
• Changed and updated Power-Up Requirements and PDB. ................................................................................................. 58
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