DS90UB928Q-Q1 Datasheet, PDF (11/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

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DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. ^{(1) (2) (3)}
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN TYP
GPIO
t_GPIO,FC
GPIO Pulse Width, Forward
Channel
See ⁽⁴⁾
t_GPIO,BC
RESET
GPIO Pulse Width, Back Channel
t_LRST
PDB Reset Low Pulse
LOOP-THROUGH MONITOR OUTPUT
See ⁽⁴⁾
See ⁽⁴⁾
GPIO[3:0],
PCLK = 5
MHz to 85
MHz
GPIO[3:0]
2/PCLK
20
PDB
2
E_W
Differential Output Eye Opening R_L = 100 Ω, Jitter freq > f/40
CMLOUTP,
Width
CMLPUTN
0.4
E_H
Differential Output Eye Height
300
FPD-LINK LVDS OUTPUT
t_TLHT
t_THLT
t_DCCJ
Low to High Transition Time
High to Low Transition Time
Cycle-to-Cycle Output Jitter
R_L = 100 Ω
PCLK = 5 MHz
PCLK = 85 MHz
TxCLK±,
0.25
TxOUT[3:0]±
0.25
TxCLK±
170
35
t_TTPn
Transmitter Pulse Position
5 MHz ≤ PCLK ≤ 85 MHz
n = [6:0] for bits [6:0]
See Figure 13
TxOUT[3:0]±
0.5 + n
Δt_TTP
Offset Transmitter Pulse Position PCLK = 85 MHz
0.1
(bit 6 - bit 0)
t_DD
Delay Latency
t_TPDD
Power Down Delay Active to OFF
t_TXZR
Enable Delay OFF to Active
FPD-LINK III INPUT
IJT
Input Jitter⁽⁵⁾
t_DDLT
Lock Time⁽⁴⁾
LVCMOS OUTPUTS
PCLK = 5 MHz to 85 MHz
Sinusoidal Jitter Frequency >
PCLK / 15
5 MHz ≤ PCLK ≤ 85 MHz
RIN±
RIN±, LOCK
147*T
900
6
6
t_CLH
Low-to-High Transition Time
t_CHL
High-to-Low Transition Time
BIST MODE
C_L = 8 pF
LOCK, PASS
3
2
t_PASS
BIST PASS Valid Time
I2S TRANSMITTER
PASS
800
t_J
Clock Output Jitter
T_I2S
I2S Clock Period
Figure 10, ^{(4) (6)}
PCLK=5 MHz to 85 MHz
MCLK
I2S_CLK,
PCLK = 5
MHz to 85
MHz
2
2/PCLK
or >77
T_HC
I2S Clock High Time
Figure 10, ⁽⁶⁾
I2S_CLK
0.35
MAX UNIT
s
µs
ms
UI
mV
0.5 ns
0.5 ns
275 ps
55
UI
UI
T
µs
ns
0.35 UI
40 ms
7 ns
5 ns
ns
ns
ns
T_I2S
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at V_DD33 = 3.3 V, V_DDIO = 1.8 V or 3.3 V, T_A = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except V_OD and ΔV_OD, which are differential voltages.
(4) Specification is ensured by design and is not tested in production.
(5) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35 × PCLK). The UI scales with PCLK frequency.
(6) I2S specifications for t_LC and t_HC pulses must each be greater than 1 PCLK period to ensure sampling and supersedes the 0.35*T_{I2S_CLK}
requirement. t_LC and t_HC must be longer than the greater of either 0.35*T_{I2S_CLK} or 2*PCLK.
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