DS90UB928Q-Q1 Datasheet, PDF (31/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

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DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
8.4 Device Functional Modes
8.4.1 Clock and Output Status
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available
on the LVCMOS and LVDS outputs. The state of the outputs is based on the OEN and OSS_SEL setting
(Table 5) or register bit (Table 8).
SERIAL
INPUT
X
X
X
Static
Static
Active
Active
INPUTS
PDB
OEN
L
X
H
L
H
L
H
H
H
H
H
H
H
H
Table 5. Output State Table
OSS_SEL
X
L
H
L
H
L
H
LOCK
Z
L or H
L or H
L
L
L
H
OUTPUTS
PASS
DATA/GPIO/I2S
TxCLKOUT/Tx
OUT[3:0]
Z
Z
Z
L
L
L
Z
Z
Z
L
L
L/OSC (Register
EN)
Previous Status
L
L
L
L
L
Valid
Valid
Valid
8.4.2 FPD-Link Input Frame and Color Bit Mapping Select
The DS90UB928Q-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2
different mapping schemes, shown in Figure 26, or MSBs on TxOUT[3], shown in Figure 27. Each frame
corresponds to a single pixel clock (PCLK) cycle. The LVDS clock output from TxCLKOUT± follows a 4:3 duty
cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending
with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 8).
TxCLKOUT
TxOUT3
TxOUT2
Previous cycle
Current cycle
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
B[6]
(bit 16)
R[1]
(bit 22)
B[5]
(bit 15)
R[0]
(bit 21)
B[4]
(bit 14)
TxOUT1
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
TxOUT0
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
Figure 26. 24-bit Color FPD-Link Mapping: LSBs on TxOUT3 (MAPSEL=L)
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