DS90UB928Q-Q1 Datasheet, PDF (39/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

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DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 38.
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 38. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus LOW. If the address doesn't
match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled HIGH.
ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the master is reading data, the master ACKs after every
data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 39 and a WRITE is shown in Figure 40.
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
AA
21
A
0
1
c
k
Data
a
c
k
P
Figure 39. Serial Control Bus — READ
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 40. Serial Control Bus — WRITE
To support I²C transactions over the BCC. the I²C Master located at the DS90UB928Q-Q1 deserializer must
support I²C clock stretching. For more information on I²C interface requirements and throughput considerations,
refer to AN-2173 I2C Communication Over FPD-Link III with Bidirectional Control Channel SNLA131.
8.6 Register Maps
ADD
(dec)
0
ADD
(hex)
0x00
Register Name
I2C Device ID
Table 8. Serial Control Bus Registers^{(1) (2)}
Bit
Register
Type
Default
(hex)
Function
Description
7:1
RW
IDx Device ID 7–bit address of Deserializer
Note: Read-only unless bit 0 is set
0
RW
ID Setting
I2C ID Setting
0: Device ID is from IDx pin
1: Register I2C Device ID overrides IDx pin
(1) Addresses not listed are reserved.
(2) Do not alter Reserved fields from their default values.
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