DS90UB928Q-Q1 Datasheet, PDF (41/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

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DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
Register Maps (continued)
Table 8. Serial Control Bus Registers^{(1) (2)} (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
3
0x03 General
7
0xF0
Reserved
Configuration 1
6
RW
Back
Back Channel CRC Generator Enable
channel
0: Disable
CRC
1: Enable (default)
Generator
Enable
5
RW
Failsafe
Outputs Failsafe Mode. Determines the pull direction
for undriven LVCMOS inputs
0: Pullup
1: Pulldown (default)
4
RW
Filter
Enable
HS, VS, DE two clock filter. When enabled, pulses
less than two full PCLK cycles on the DE, HS, and VS
inputs will be rejected
0: Filtering disable
1: Filtering enable (default)
3
RW
I2C Pass-
Through
I2C Pass-Through Mode
Read/Write transactions matching any entry in the
DeviceAlias registers will be passed through to the
remote serializer I2C interface.
0: Pass-Through Disabled (default)
1: Pass-Through Enabled
2
RW
Auto ACK
Automatically Acknowledge I2C transactions
independent of the forward channel Lock state.
0: Disable (default)
1: Enable
1
RW
DE Gate
RGB
Gate RGB data with DE signal. In DS90UH928, RGB
data is gated with DE in order to allow packetized
audio and block unencrypted data. In DS90UB928 or
in Backward Compatibility mode, RGB data is not
gated with DE by default. However, to enable
packetized audio in DS90UB928, this bit must be set.
This bit has no effect in DS90UH928.
0: Pass RGB data independent of DE in Backward
Compatibility mode or interfacing to DS90UB925 or
DS90UB927
1: Gate RGB data with DE in Backward Compatibility
mode or interfacing to DS90UB925 or DS90UB927
0
Reserved
4
0x04 BCC Watchdog 7:1
RW
Control
0xFE
BCC
Watchdog
Timer
BCC Watchdog Timer The watchdog timer allows
termination of a control channel transaction if it fails to
complete within a programmed amount of time. This
field sets the Bidirectional Control Channel Watchdog
Timeout value in units of 2 ms. This field should not
be set to 0.
0
RW
BCC
Watchdog
Disable
Disable Bidirectional Control Channel Watchdog
Timer
0: Enable (default)
1: Disable
5
0x05 I2C Control 1
7
RW
0x1E I2C Pass- I2C Pass-Through All Transactions. Pass all local I2C
All
transactions to the remote serializer.
0: Disable (default)
1: Enable
6:4
RW
I2C SDA
Hold
Internal I2C SDA Hold Time
This field configures the amount of internal hold time
is provided for the SDA input relative to the SCL input.
Units are 50 ns.
3:0
RW
I2C Filter
Depth
I2C Glitch Filter Depth
This field configures the maximum width of glitch
pulses on the SCL and SDA inputs that will be
rejected. Units are 5 ns.
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