DS90UB928Q-Q1 Datasheet, PDF (25/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

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Feature Description (continued)
DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
8-bit in / 8 bit out
Gray level Data Out
Entry
(8-bits)
0 00000000b
1 00000001b
2 00000011b
3 00000011b
4 00000110b
5 00000110b
6 00000111b
7 00000111b
8 00001000b
9 00001010b
10 00001001b
11 00001011b
6-bit in / 6 bit out
Gray level Data Out
Entry
(8-bits)
0 00000000b
1 N/A
2 N/A
3 N/A
4 00000100b
5 N/A
6 N/A
7 N/A
8 00001000b
9 N/A
10 N/A
11 N/A
6-bit in / 8 bit out
Gray level Data Out
Entry
(8-bits)
0 00000001b
1 N/A
2 N/A
3 N/A
4 00000110b
5 N/A
6 N/A
7 N/A
8 00001011b
9 N/A
10 N/A
11 N/A
248 11111010b
249 11111010b
250 11111011b
251 11111011b
252 11111110b
253 11111101b
254 11111101b
255 11111111b
248 11111000b
249 N/A
250 N/A
251 N/A
252 11111100b
253 N/A
254 N/A
255 N/A
248 11111010b
249 N/A
250 N/A
251 N/A
252 11111111b
253 N/A
254 N/A
255 N/A
Figure 22. White Balance LUT Configuration
8.3.11.2 Adaptive Hi-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per sub-pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled via serial control bus register. Two FRC functional blocks are available, and may be independently
enabled. FRC1 precedes the white balance LUT, and is intended to be used when 24-bit data is being driven to
an 18-bit display with a white balance LUT that is calibrated for an 18-bit data source. The second FRC block,
RC2, follows the white balance block and is intended to be used when fine adjustment of color temperature is
required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT
calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to device control registers via the serial bus
interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-
pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 23. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated
LSBs are “001”.
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