DS90UB928Q-Q1 Datasheet, PDF (50/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
www.ti.com
Register Maps (continued)
Table 8. Serial Control Bus Registers^{(1) (2)} (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
41
0x29 FRC Control
7
RW
0x00
Timing
Mode
Select
Select Display Timing Mode
0: DE only Mode (default)
1: Sync Mode (VS,HS)
6
RW
HS Polarity Horizontal Sync Polarity Select
0: Active High (default)
1: Active Low
5
RW
VS Polarity Vertical Sync Polarity Select
0: Active High (default)
1: Active Low
4
RW
DE Polarity Data Enable Sync Polarity Select
0: Active High (default)
1: Active Low
3
RW
FRC2
Enable
FRC2 Enable
0: FRC2 disable (default)
1: FRC2 enable
2
RW
FRC1
Enable
FRC1 Enable
0: FRC1 disable (default)
1: FRC1 enable
1
RW
Hi-FRC2
Enable
Hi-FRC2 Enable
0: Hi-FRC2 enable (default)
1: Hi-FRC2 disable
0
RW
Hi-FRC1
Enable
Hi-FRC1 Enable
0: Hi-FRC1 enable (default)
1: Hi-FRC1 disable
42
0x2A White Balance 7:6
RW
Control
0x00
Page
Setting
Control/LUT Setting Page Select
00: Configuration Registers (default)
01: Red LUT
10: Green LUT
11: Blue LUT
5
RW
White
Balance
Enable
White Balance Enable
0: White Balance Disabled (default)
1: White Balance Enabled
4
RW
LUT Reload Enable LUT Reload
Enable
0: Reload Disable (default)
1: Reload Enable
3:0
Reserved
43
0x2B I2S Control
7
RW
0x00 I2S PLL
Override I2S PLL
Override 0: PLL override disabled (default)
1: PLL override enabled
6
RW
I2S PLL
Enable
Enable I2S PLL
0: I2S PLL is on for I2S data jitter cleaning (default)
1: I2S PLL is off. No jitter cleaning
5:1
Reserved
0
RW
I2S Clock
Edge
I2S Clock Edge Select
0: I2S Data is strobed on the Falling Clock Edge
(default)
1: I2S Data is strobed on the Rising Clock Edge
50
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Product Folder Links: DS90UB928Q-Q1