DS90UB928Q-Q1 Datasheet, PDF (38/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
8.5 Programming
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8.5.1 Serial Control Bus
The DS90UB928Q-Q1 may also be configured by the use of an I²C compatible serial control bus. Multiple
devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a
resistor divider (R1 and R2 — see Figure 37) connected to the IDx pin.
VDD33
HOST
SCL
SDA
VDD33
R1
VR2
IDx
4.7kQ
4.7kQ
R2
DES
SCL
SDA
To other
Devices
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Figure 37. Serial Control Bus Connection
The serial control bus consists of two signals and an address configuration pin. SCL is a Serial Bus Clock
Input/Output. SDA is the Serial Bus Data Input/Output signal. Both SCL and SDA signals require an external
pullup resistor to V_DD33 or V_DDIO = 3 V to 3.6 V. For most applications, a 4.7 kΩ pullup resistor to V_DD33 is
recommended. The signals are either pulled HIGH, or driven LOW.
The IDx pin configures the control interface to one of 10 possible device addresses. Use a pullup resistor and a
pulldown resistor to set the appropriate voltage ratio between the IDx input pin (V_R2) and V_DD33, each ratio
corresponding to a specific device address. See .
NO.
IDEAL RATIO
V_R2 / V_DD33
1
0
2
0.302
3
0.345
4
0.388
5
0.428
6
0.476
7
0.517
8
0.560
9
0.605
10
0.768
Table 7. Serial Control Bus Addresses for IDx
IDEAL V_R2
(V)
0
0.995
1.137
1.282
1.413
1.570
1.707
1.848
1.997
2.535
SUGGESTED
RESISTOR R1 kΩ
(1% tol)
OPEN
22.6
21.5
20.0
18.7
17.4
15.4
15.0
13.7
9.09
SUGGESTED
RESISTOR R2 kΩ
(1% tol)
40.2
9.76
11.3
12.7
14.0
15.8
16.5
19.1
21.0
30.1
ADDRESS 7'b
0x2C
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
ADDRESS 8'b
0x58
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
38
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