DS90UB928Q-Q1 Datasheet, PDF (40/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
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Register Maps (continued)
Table 8. Serial Control Bus Registers^{(1) (2)} (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
1
0x01 Reset
7:3
0x04
Reserved
2
RW
BC Enable Back Channel Enable
0: Disable
1: Enable
1
RW
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
0: Normal operation (default)
1: Reset
0
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
0: Normal operation (default)
1: Reset
2
0x02 General
7
RW
0x00 OEN
Configuration 0
LVCMOS Output Enable. Self-clearing on loss of
LOCK
0: Disable, Tristate Outputs (default)
1: Enable
6
RW
OEN/OSS_ Output Enable and Output Sleep State Select override
SEL
0: Disable over-write (default)
Override 1: Enable over-write
5
RW
Auto Clock
Enable
OSC Clock Output. Enable On loss of lock, OSC
clock is output onto TxCLK±
0: Disable (default)
1: Enable
4
RW
OSS_SEL
Output Sleep State Select. Enable Select to control
output state during lock low period
0: Disable, Tri-State Outputs (default)
1: Enable
3
RW
BKWD
Override
Backwards Compatibility Mode Override
0: Use MODE_SEL pin (default)
1: Use register bit to set BKWD mode
2
RW
BKWD
Mode
Backwards Compatibility Mode Select
0: Backwards Compatibility Mode disabled (default)
1: Backwards Compatibility Mode enabled
1
RW
LFMODE
Override
Low Frequency Mode Override
0: Use LFMODE pin (default)
1: User register bit to set LFMODE
0
RW
LFMODE
Low Frequency Mode
0: 15 MHz ≤ PCLK ≤ 85 MHz (default)
1: 5 MHz ≤ PCLK < 15 MHz
40
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