DAC8728_14 Datasheet, PDF (7/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
www.ti.com
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
ELECTRICAL CHARACTERISTICS: Single-Supply
All specifications at T_A = T_MIN to T_MAX, AV_DD = +32V, AV_SS = 0V, DV_DD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x =
DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
PARAMETER
CONDITIONS
STATIC PERFORMANCE
Resolution
Linearity error
Measured by line passing through codes 0100h and FFFFh
Differential linearity error
Measured by line passing through codes 0100h and FFFFh
Unipolar zero error
Unipolar zero error TC
T_A = +25°C, before user calibration, gain = 6, code = 0100h
T_A = +25°C, before user calibration, gain = 4, code = 0100h
T_A = +25°C, after user calib., gain = 4 or 6, code = 0100h
Gain = 4 or 6, code = 0100h
Gain error
Gain error TC
T_A = +25°C, gain = 6
T_A = +25°C, gain = 4
Gain = 4 or 6
Full-scale error
Full-scale error TC
T_A = +25°C, before user calibration, gain = 6, code = FFFFh
T_A = +25°C, before user calibration, gain = 4, code = FFFFh
T_A = +25°C, after user calib., gain = 4 or 6, code = FFFFh
Gain = 4 or 6, code = FFFFh
DC crosstalk⁽¹⁾
Measured channel at code = 8000h, full-scale change on any
other channel
ANALOG OUTPUT (V_OUT-0 to V_OUT-7)⁽²⁾
Voltage output⁽³⁾
V_REF = +5V
V_REF = +1.5V
Output impedance
Code = 8000h
Short-circuit current⁽⁴⁾
Load current
See Figure 89 and Figure 90
Output drift vs time
Capacitive load stability
T_A = +25°C, device operating for 500 hours, full-scale output
T_A = +25°C, device operating for 1000 hours, full-scale output
To 0.03% of FSR, C_L = 200pF, R_L= 10kΩ, code from 0100h to
FFFFh and FFFFh to 0100h
Settling time
To 1 LSB, C_L = 200pF, R_L = 10kΩ, code from 0100h to FFFFh
and FFFFh to 0100h
To 1 LSB, C_L = 200pF, R_L = 10kΩ, code from 7F00h to 8100h
and 8100h to 7F00h
Slew rate⁽⁵⁾
Power-on delay⁽⁶⁾
Power-down recovery time
Digital-to-analog glitch⁽⁷⁾
From IOV_DD ≥ +1.8V and DV_DD ≥ +2.7V to CS low
Code from 7FFFh to 8000h and 8000h to 7FFFh
Glitch impulse peak amplitude Code from 7FFFh to 8000h and 8000h to 7FFFh
DAC8728
MIN
TYP
16
±1
±0.5
±1
±1
±0.5
0.2
0
0
±10
±3
3.4
4.3
10
15
6
6
200
50
4
5
MAX
UNIT
Bits
±4
LSB
±1
LSB
±10
LSB
±15
LSB
LSB
±3 ppm FSR/°C
±10
LSB
±15
LSB
±3 ppm FSR/°C
±10
LSB
±15
LSB
LSB
±3 ppm FSR/°C
LSB
+30
V
+9
V
0.5
Ω
mA
mA
ppm of FSR
ppm of FSR
500
pF
μs
μs
μs
V/μs
μs
μs
nV-s
mV
(1) The DAC outputs are buffered by op amps that share common AV_DD and AV_SS power supplies. DC crosstalk indicates how much dc
change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With
high-impedance loads, the effect is virtually immeasurable. Multiple AV_DD and AV_SS terminals are provided to minimize dc crosstalk.
(2) Specified by design.
(3) The analog output range of V_OUT-0 to V_OUT-7 is equal to (6 × V_REF) for gain = 6. The maximum value of the analog output must not be
greater than (AV_DD – 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted.
(4) When the output current is greater than the specification, the current is clamped at the specified maximum value.
(5) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(6) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(7) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format.
Copyright © 2009, Texas Instruments Incorporated
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