DAC8728_14 Datasheet, PDF (38/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
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GENERAL-PURPOSE INPUT/OUTPUT PIN (GPIO)
The GPIO pin is a general-purpose, bidirectional, digital input/output, as shown in Figure 97. When the GPIO pin
acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin
output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'.
Note that a pull-up resistor to IOV_DD is required when using the GPIO pin as an output. When the GPIO pin acts
as an input, the digital value on the pin is acquired by reading the GPIO bit. After power-on reset, or any forced
hardware or software reset, the GPIO bit is set to '1', and is in a high-impedance state. If not used, the GPIO pin
must be tied to either DGND or to IOV_DD through a pull-up resistor. Leaving the GPIO pin floating can cause high
IOV_DD supply currents.
+IOV_DD
Bit GPIO (when writing)
Enable
GPIO
Bit GPIO (when reading)
Figure 97. GPIO Pin
BUSY Pin
The BUSY pin is an open-drain output. When the correction engine runs, the GBF bit in the Configuration
Register is set and the BUSY pin is low. When multiple DAC8728 devices may be used in one system, the BUSY
pins can be tied together. When each device has finished updating the DAC Data Register, the respective BUSY
pin is released. If another device has not finished updating the DAC Data Register, it will hold BUSY low. This
configuration is useful when it is required that no DAC in any device is updated until all other DACs are ready.
ANALOG OUTPUT PIN (CLR)
The CLR pin is an active low input that should be high for normal operation. When this pin is in logic '0', all V_OUT
outputs connect to AGND-x through internal 15kΩ resistors and are cleared to 0 V, and the output buffer is in a
Hi-Z state. While CLR is low, all LDAC pulses are ignored. When CLR is taken high again while the LDAC is
high, the DAC outputs remain cleared until LDAC is taken low. However, if LDAC is tied low, taking CLR back to
high sets the DAC output to the level defined by the value of the DAC latch. The contents of the Zero Registers,
Gain Registers, Input Data Registers, DAC Data Registers, and DAC latches are not affected by taking CLR low.
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