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| DAC8728_14 Datasheet, PDF (12/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER | |||
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DAC8728
SBAS466A â JUNE 2009 â REVISED NOVEMBER 2009
TIMING DIAGRAMS
www.ti.com
CS
R/W
A4:A0
D15:D0
t8
t9
t10
t11
t13
Hi-Z
t12
t14
Hi-Z
Figure 2. Read Operation
space
CS
R/W
A4:A0
t1
CS
t2
t3
R/W
t4
t5
A4:A0
D15:D0
Hi-Z
Hi-Z
t6
t7
Write Operation 1:
1. Writing to the Configuration Register, Offset Register,
Monitor Register, GPIO Register.
2. Writing to the DAC Input Registers, Zero Registers, and
Gain Registers in Asynchronous mode (LDAC pin is tied low).
Figure 3. Write Operation 1
t1
t2
t3
t4
t5
D15:D0
Hi-Z
t6
LDAC
Hi-Z
t7
t15
t16
LD bit can be set to replace LDAC
to update the DAC output
Write Operation 2:
Writing to the DAC Input Data Registers, Zero Registers, and
Gain Registers when the correction engine is disabled and
DAC outputs are updated in Synchronous mode.
Figure 4. Write Operation 2
CS
BUSY
t18
t17
t16
LDAC
LD bit can be set to replace LDAC
to update the DAC output
Write Operation 3:
Writing to the DAC Input Data Registers, Zero Registers, and Gain Registers when the correction engine is
enabled (SCE = 1) and the DAC outputs are updated in Synchronous mode. The update trigger (either LDAC
or the LD bit) activates after the correction completes.
Figure 5. Write Operation 3
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Copyright © 2009, Texas Instruments Incorporated
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