DAC8728_14 Datasheet, PDF (33/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
www.ti.com
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
USER-CALIBRATION FOR ZERO ERROR AND GAIN ERROR
The DAC8728 implements a digital user-calibration function that allows for trimming gain and zero errors on the
entire signal chain. This function can eliminate the need for external adjustment circuits. Each DAC channel has
a Zero Register and Gain Register. Using the correction engine, the data from the Input Data Register are
operated on by a digital adder and multiplier controlled by the contents of Zero and Gain registers, respectively.
The calibrated DAC data are then stored in the DAC Data Register where they are finally transferred into the
DAC latch and set the DAC output. Each time the data are written to the Input Data Register (or to the Gain or
Zero registers), the data in the Input Data Register are corrected, and the results automatically transferred to
DAC Data Register.
The range of the gain adjustment coefficient is 0.5 to 1.5. The range of the zero adjustment is –32768 LSB to
+32767 LSB, or ±50% of full scale.
There is only one correction engine in the DAC8728, which is shared among all channels. Each channel has an
individual busy flag (BF-x) in the Busy Flag register. When the channel is accessed, the respective BF-x bit is set
if either the Input Data Register, Zero Register, or Gain Register are written to. When the DAC data are adjusted
by the correction engine and transferred into DAC Data Register, the BF-x bit is cleared. It takes approximately
500ns per channel for the correction to complete.
The correction engine calibrates the individual channels according to priority. DAC-0 has the highest priority,
while DAC-7 has the lowest. Correction of lower-priority channels is not performed until correction of
higher-priority channels completes. Repeatedly accessing higher-priority channels may block the correction of
lower-priority channels. Table 1 lists the correction engine channel priority.
Table 1. Correction Engine Priority
CHANNEL
DAC-0
DAC-1
DAC-2
DAC-3
DAC-4
DAC-5
DAC-6
DAC-7
PRIORITY
1 (highest)
2
3
4
5
6
7
8 (lowest)
The device also provides a global busy flag (GBF) and a logic output from the BUSY pin to indicate the
correction engine status. When the correction engine is running, the GBF bit is set ('1'), and the BUSY pin is low.
When the engine stops, GBF is cleared ('0'), and the BUSY pin goes high (or Hi-Z if no pull-up resistor is used).
Note that when the correction engine is disabled, the GBF bit is always cleared, and the BUSY pin is always in a
Hi-Z state.
To avoid any potential conflicts caused by the correction process, the input data must be written properly. Either
one of the following approaches can be used to update the DAC Input Data Register, Zero Register, or Gain
Register:
1. Writing to any channel when the BUSY pin is high or when the GBF bit = '0'.
2. Writing to an individual channel when the corresponding BF-x bit = '0'.
3. Tracking the correction time. It takes approximately 500ns to correct one channel for each input data, zero or
gain change.
The individual channel can be rewritten only if the corrections are completed for that channel and for all other
channels that have higher priority. For example, if DAC-0, DAC-1, and DAC-2 are written to first, and then DAC-1
is written to again, the second writing to DAC-1 is not permitted until the correction of the first DAC-1 writing is
complete (that is, approximately 1000ns after writing to DAC-0, or 500ns after the first writing to DAC-1).
However, if writing to DAC-0, DAC-1, DAC-2, and then DAC-2 again, the second writing of DAC-2 is prohibited
until the correction for the first writing to DAC-2 is complete (that is, approximately 1500ns after writing to DAC-0,
or 500ns after the first writing to DAC-2).
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8728
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