DAC8728_14 Datasheet, PDF (45/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
www.ti.com
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
Zero Register n (where n = 0 to 7). Default = 0000h.
The Zero Register stores the user-calibration data that are used to eliminate the offset error, as shown in
Table 14. The data are 16 bits wide, 1 LSB/step, and the total adjustment is –32768 LSB to +32767 LSB, or
±50% of full-scale range. The Zero Register uses a twos complement data format.
Table 14. Zero Register
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Z15 Z14 Z13 Z12 Z11 Z10 Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Z15:Z0—OFFSET BITS
7FFFh
7FFEh
••• ••• •••
0001h
0000h
FFFFh
••• ••• •••
8001h
8000h
ZERO ADJUSTMENT
+32767 LSB
+32766 LSB
••• ••• •••
+1 LSB
0 LSB (default)
–1 LSB
••• ••• •••
–32767 LSB
–32768 LSB
Gain Register n (where n = 0 to 7). Default = 8000h.
The Gain Register stores the user-calibration data that are used to eliminate the gain error, as shown in
Table 15. The data are 16 bits wide, 0.0015% FSR/step, and the total adjustment range 0.5 to 1.5. The Gain
Register uses a straight binary data format.
Table 15. Gain Register
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
G15 G14 G13 G12 G11 G10 G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
G15:G0—GAIN-CODE BITS
FFFFh
FFFEh
••• ••• •••
8001h
8000h
7FFFh
••• ••• •••
0001h
0000h
GAIN ADJUSTMENT COEFFICIENT
1.499985
1.499969
••• ••• •••
1.000015
1 (default)
0.999985
••• ••• •••
0.500015
0.5
Copyright © 2009, Texas Instruments Incorporated
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