DAC8728_14 Datasheet, PDF (10/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
PAG PACKAGE
TQFP-64
(TOP VIEW)
PIN CONFIGURATIONS
D13 1
D14 2
D15 3
V_MON 4
V_OUT-3 5
REF-A 6
V_OUT-2 7
AV_DD 8
AGND-A 9
V_OUT-1 10
AV_SS 11
OFFSET-A 12
V_OUT-0 13
NC 14
USB/BTC 15
BUSY 16
DAC8728
48 D2
47 D1
46 D0
45 NC
44 V_OUT-4
43 REF-B
42 V_OUT-5
41 AV_DD
40 AGND-B
39 V_OUT-6
38 AV_SS
37 OFFSET-B
36 V_OUT-7
35 NC
34 RSTSEL
33 GPIO
D13 1
D14 2
D15 3
V_MON 4
V_OUT-3 5
REF-A 6
V_OUT-2 7
AV_DD 8
AGND-A 9
V_OUT-1 10
AV_SS 11
OFFSET-A 12
V_OUT-0 13
USB/BTC 14
RTQ PACKAGE
QFN-56
(TOP VIEW)
DAC8728
www.ti.com
42 D3
41 D2
40 D1
39 D0
38 NC
37 VOUT-4
36 REF-B
35 VOUT-5
34 AVDD
33 AGND-B
32 VOUT-6
31 AVSS
30 OFFSET-B
29 VOUT-7
PIN
NAME
D13
D14
D15
V_MON
V_OUT-3
REF-A
V_OUT-2
AV_DD
AGND-A
V_OUT-1
AV_SS
OFFSET-A
V_OUT-0
USB/BTC
BUSY
CLR
PIN NO.
QFN-56
TQFP-64
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
15
15
16
16
17
(1) The thermal pad is internally connected to
the substrate. This pad can be connected
to AV_SS or left floating. Keep the thermal
pad separate from the digital ground, if
possible.
PIN DESCRIPTIONS
I/O
DESCRIPTION
I/O Data bit 13
I/O Data bit 14
I/O Data bit 15
O
Analog monitor output. This pin is either in Hi-Z status, or connected to one of the DAC outputs,
reference buffer outputs, or offset DAC outputs, depending on the content of the Monitor Register.
O DAC-3 output
I Group A⁽¹⁾ reference input
O DAC-2 output
I Positive analog power supply
I Group A⁽¹⁾ analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND.
O DAC-1 output
I Negative analog power supply. Connect to AGND in single-supply operation.
O
OFFSET DAC-A analog output. Must be connected to AGND-A during single power-supply operation
(AV_SS = 0V). This pin is not intended to drive an external load.
O DAC-0 output
I
Input data format selection. Input data are in straight binary format when connected to DGND or in twos
complement format when connected to IOV_DD. Command data are always in straight binary format.
O
This pin is an open drain and requires an external pullup resistor. BUSY goes low when the correction
engine is running; see the Busy Pin section for details.
Level trigger. When the CLR pin is logic '0', all V_OUT-X pins connect to AGND-x through switches and an
I internal 15kΩ resistor. When the CLR pin is logic '1' and LDAC is logic '0', all V_OUT-X pins connect to the
amplifier outputs.
(1) Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7.
10
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