DAC8728_14 Datasheet, PDF (15/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
www.ti.com
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
TIMING CHARACTERISTICS^{(1) (2) (3) (4) (5)}
At –40°C to +105°C, DV_DD = +3V to +5V, and IOV_DD = +1.8V, unless otherwise noted.
PARAMETER
MIN
MAX
t₁
CS width for write operation
t₂
Delay from R/W falling edge to CS falling edge
t₃
Delay from CS rising edge to R/W rising edge
t₄
Delay from address valid to CS falling edge
t₅
Delay from CS rising edge to address change
t₆
Delay from data valid to CS rising edge
t₇
Delay from CS rising to data change
t₈
CS width for read operation
t₉
Delay from R/W rising edge to CS falling edge
t₁₀
Delay from CS rising edge to R/W falling edge
t₁₁
Delay from address valid to CS falling edge
t₁₂
Delay from CS rising to address change
t₁₃
Delay from CS falling edge to data valid
t₁₄
Delay from CS rising to data bus off (Hi-Z)
t₁₅
Delay from CS rising edge to LDAC falling edge
t₁₆
LDAC pulse width
t₁₇
Delay from LDAC rising edge to next CS rising edge
t₁₈
Delay from BUSY rising edge to next LDAC falling edge
t₁₉
Delay from CS rising edge to next LDAC falling edge
t₂₀
Delay from CS rising edge to BUSY falling edge
t₂₁
Delay from LDAC falling edge to BUSY rising edge
35
2
2
12
0
35
5
60
2
2
12
0
50
2
5
10
30
0
50
30
50
(1) Specified by design; not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) Rise and fall times of all digital input signals are 8ns.
(4) Rise and fall times of all digital outputs are 12ns for a 10pF capacitor load.
(5) For sequential writes to the same address, there must be a minimum of 50ns between the CS rising edges.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2009, Texas Instruments Incorporated
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