DAC8728_14 Datasheet, PDF (41/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
www.ti.com
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
MONITOR OUTPUT PIN (V_MON)
The V_MON pin is the channel monitor output. It monitors either of the DAC outputs, offset DAC outputs, or
reference buffer outputs. The channel monitor function consists of an analog multiplexer addressed via the
parallel interface, allowing any channel output, reference buffer output, or offset DAC output to be routed to the
V_MON pin for monitoring using an external ADC. The monitor function is controlled by the Monitor Register, which
allows the monitor output to be enabled or disabled. When disabled, the monitor output is high-impedance;
therefore, several monitor outputs may be connected in parallel with only one enabled at a time.
Note that the multiplexer is implemented as a series of analog switches. Care should be taken to ensure the
maximum current from the V_MON pin must not be greater than the given specification because this could
conceivably cause a large amount of current to flow from the input of the multiplexer (that is, from V_OUT-X) to the
output of the multiplexer (V_MON). Refer to the Monitor Register section and Table 12 for more details.
POWER-DOWN MODE
The DAC8728 is implemented with a power-down function to reduce power consumption. Either the entire device
or each individual group can be put into power-down mode. If the proper power-down bit (PD-x) in the
Configuration Register is set to '1', the individual group is put into power down mode. During power-down mode,
the analog outputs (V_OUT-0 to V_OUT-7) connect to AGND-X through an internal 15kΩ resistor, and the output
buffer is in Hi-Z status. When the entire device is in power-down, the bus interface remains active in order to
continue communication and receive commands from the host controller, but all other circuits are powered down.
The host controller can wake the device from power-down mode and return to normal operation by clearing the
PD-x bit; it takes 200μs or less for recovery to complete.
POWER-ON RESET SEQUENCING
The DAC8728 permanently latches the status of some of the digital pins at power-on. These digital levels should
be well-defined before or while the digital supply voltages are applied. Therefore, it is advised to have a pull up
resistor to IOV_DD or DGND for the digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL) to ensure that
these levels are set correctly while the digital supplies are raised.
For proper power-on initialization of the device, IOV_DD and the digital pins must be applied before or at the same
time as DV_DD. If possible, it is preferred that IOV_DD and DV_DD can be connected together in order to simplify the
supply sequencing requirements. Pull-up resistors should go to either supply. AV_DD should be applied after the
digital supplies (IOV_DD and DV_DD) and digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL). AV_SS can
be applied at the same time as or after AV_DD. The REF-x pins must be applied last.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8728
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