DAC8728_14 Datasheet, PDF (43/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
www.ti.com
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
INTERNAL REGISTERS
The DAC8728 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data
Registers, the Zero Registers, the Gain Registers, the DAC Data Registers, and the Busy Flag Register, and are
described in the following section.
The Configuration Register specifies which actions are performed by the device. Table 11 shows the details.
BIT
D15
D14
D13
D12
D11
D10
D9
(Read
Only)
D8
D7
D6:D0
Table 11. Configuration Register (Default = 8000h)
NAME
A/B
LD
RST
PD-A
PD-B
SCE
GBF
GAIN-A
GAIN-B
—
DEFAULT
VALUE
1
0
0
0
0
0
0
0
0
0
DESCRIPTION
A/B bit.
When A/B = '0', reading DAC-x returns the value in the Input Data Register.
When A/B = '1', reading DAC-x returns the value in the DAC Data Register.
When the correction engine is enabled, the data returned from the Input Data Register are the original data written to the
bus, and the value in the DAC Data Register is the corrected data.
Synchronously update DAC bits.
When LDAC is tied high, setting LD = '1' at any time after the write operation and the correction process complete
synchronously updates all DAC latches with the content of the corresponding DAC Data Register, and sets V_OUT to a new
level. The DAC8728 updates the DAC latch only if it has been accessed since the last time LDAC was brought low or the
LD bit was set to '1', thereby eliminating unnecessary glitch. Any DACs that were not accessed are not reloaded. After
updating, the bit returns to '0'. When the LDAC pin is tied low, this bit is ignored. When the correction engine is off, the LD
bit can be issued any time after the write operation is finished, and the DAC latch is immediately updated when CS goes
high.
Software reset bit.
Set the RST bit to '1' to reset the device; functions the same as a hardware reset. After reset completes, the RST bit
returns to '0'.
Power-down bit for Group A.
Setting the PD-A bit to '1' places Group A (DAC-0, DAC-1, DAC-2, and DAC-3) into power-down mode. All output buffers
are in Hi-Z and all analog outputs (V_OUT-X) connect to AGND-A through an internal 15kΩ resistor.
Setting the PD-A bit to '0' returns group A to normal operation.
Power-down bit for Group B.
Setting the PD-B bit to '1' places Group B (DAC-4, DAC-5, DAC-6, and DAC-7) into power-down operation. All output
buffers are in Hi-Z and all analog outputs (V_OUT-X) connect to AGND-B through an internal 15kΩ resistor.
Setting the PD-B bit to '0' returns group B to normal operation.
System-calibration enable bit.
Set the SCE bit to '1' to enable the correction engine. When the engine is enabled, the input data are adjusted by the
correction engine according to the contents of the corresponding Gain Register and Zero Register. The results are
transferred to the corresponding DAC Data Register, and finally loaded into the DAC latch, which sets the V_OUT-x pin
output level.
Set the SCE bit to '0' to turn off the correction engine. When the engine is turned off, the input data are transferred to the
corresponding DAC Data Register, and then loaded into the DAC latch, which sets the output voltage. Refer to the User
Calibration for Zero Error and Gain Error section for details.
Global correction engine busy flag.
GBF = '1' when the correction engine is running, indicating that at least one channel has not been corrected.
GBF = 0' 'when the correction engine stops, indicating that no more correction is needed.
When the SCE bit = '0', GBF is always cleared ('0').
Gain bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3).
Set the GAIN-A bit to '0' for an output span = 6 × REF-A.
Set the GAIN-A bit to '1' for an output span = 4 × REF-A.
Updating this bit to a new value automatically resets the Offset DAC-A Register to its factory-trimmed value for the new
gain setting.
Gain bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7).
Set the GAIN-B bit to '0' for an output span = 6 × REF-B.
Set the GAIN-B bit to '1' for an output span = 4 × REF-B.
Updating this bit to a new value automatically resets the Offset DAC-B Register to its factory-trimmed value for the new
gain setting.
Don't care. Writing to these bits has no effect; reading these bits returns '0'.
Copyright © 2009, Texas Instruments Incorporated
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