DAC8728_14 Datasheet, PDF (42/56 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER

DAC8728
SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009
www.ti.com
PARALLEL INTERFACE
The DAC8728 interfaces with microprocessors using a 16-bit data bus. The interface is double-buffered, allowing
simultaneous updating of all DACs. Each DAC has an input data register, DAC data register, user-calibration
gain register, user-calibration zero register, and DAC latch. When user calibration is enabled, the input data
register receives data from the data bus, the DAC Data Register stores the data after internal calibration, and the
DAC latch sets the analog output level. When user calibration is disabled (default), the DAC data register stores
data from the data bus, and the DAC latch sets the analog output level. Five address lines (A0:A4) select which
DAC or auxiliary register is addressed. Table 10 shows the register map.
Table 10. Register Map
ADDRESS BITS
A4 A3 A2 A1 A0 D15 D14 D13
0 0 0 0 0 A/B LD RST
0
0
0
0
1
DAC-
7
DAC- DAC-
6
5
0 0 0 1 0 GPIO
00011
00100
0 0 1 0 1 BF-7 BF-6 BF-5
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
11000
10001
11001
10010
11010
10011
11011
10100
11100
10101
11101
10110
11110
10111
11111
DATA BITS
D12 D11 D10 D9
D8
D7
D6
D5 D4 D3:D0
PD-A PD-B SCE GBF GAIN-A GAIN-B
Don't Care⁽¹⁾
DAC-
4
DAC-
3
DAC-
2
DAC-
1
DAC-0
Offset
DAC-A
Don't Care⁽¹⁾
Offset
DAC-B
Ref Ref
Buffer Buffer
-A
-B
Don't
Care ⁽¹⁾
D15:D0, default = 39322 (999Ah)
D15:D0 , default = 39322 (999Ah)
BF-4 BF-3 BF-2 BF-1 BF-0
Reserved ⁽²⁾
Reserved ⁽²⁾
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Don't Care⁽¹⁾
REGISTER
Configuration
Register
Monitor Register
GPIO Register
Offset DAC-A
Data Register
Offset DAC-B
Data Register
Busy Flag
Register
Reserved
Reserved
DAC-0
DAC-1
DAC-2
DAC-3
DAC-4
DAC-5
DAC-6
DAC-7
Zero Register-0
Gain Register-0
Zero Register-1
Gain Register-1
Zero Register-2
Gain Register-2
Zero Register-3
Gain Register-3
Zero Register-4
Gain Register-4
Zero Register-5
Gain Register-5
Zero Register-6
Gain Register-6
Zero Register-7
Gain Register-7
(1) Writing to a Don't Care bit has no effect; reading the bit returns '0'.
(2) Writing to a reserved bit has no effect; reading the bit returns '0'.
42
Submit Documentation Feedback
Product Folder Link(s): DAC8728
Copyright © 2009, Texas Instruments Incorporated