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| DAC8562SDSCT Datasheet, PDF (7/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON | |||
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TIMING DIAGRAM
t1
t2
SCLK
t4
t5
t6
t7
SYNC
t10
t9
DIN
DB23
LDAC(1)
t3
t8
DB0
t12
t11
DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D â AUGUST 2010 â REVISED AUGUST 2012
LDAC(2)
t13
CLR
t14
VOUT
(1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section.
(2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.
Figure 1. Serial Write Operation
TIMING REQUIREMENTS(1)(2)
At AVDD = 2.7 V to 5.5 V and over â40°C to 125°C (unless otherwise noted).
PARAMETER
t1
SCLK falling edge to SYNC falling edge (for successful write operation)
t2 (3)
SCLK cycle time
t3
SYNC rising edge to 23rd SCLK falling edge (for successful SYNC interrupt)
t4
Minimum SYNC HIGH time
t5
SYNC to SCLK falling edge setup time
t6
SCLK LOW time
t7
SCLK HIGH time
t8
SCLK falling edge to SYNC rising edge
t9
Data setup time
t10
Data hold time
t11
SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode
t12
LDAC pulse duration, LOW time
t13
CLR pulse duration, LOW time
t14
CLR falling edge to start of VOUT transition
DAC756x/DAC816x/DAC856x
MIN
TYP
MAX
10
20
13
80
13
8
8
10
6
5
5
10
80
100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VINL + VINH)/2.
(2) See the Serial Write Operation timing diagram (Figure 1).
(3) Maximum SCLK frequency is 50 MHz at AVDD = 2.7 V to 5.5 V.
Copyright © 2010â2012, Texas Instruments Incorporated
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Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563
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