DAC8562SDSCT Datasheet, PDF (32/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
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Input Shift Register
The input shift register (SR) of the DAC856x, DAC816x, and DAC756x is 24 bits wide (as shown in Table 8,
Table 9, and Table 10, respectively), and consists of two don’t care bits (DB23 to DB22), three command bits
(DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to DB0). The 16 data bits comprise
the 16-, 14-, or 12-bit input code.
X ⁽¹⁾ X
DB23
Table 8. DAC856x Data Input Register Format
Command
Address
Data
C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB0
(1) X' denotes don't care bits.
XX
DB23
Table 9. DAC816x Data Input Register Format
Command
Address
Data
C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XX
DB0
Table 10. DAC756x Data Input Register Format
Command
Address
Data
X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
DB23
DB0
The DAC856x, DAC816x, and DAC756x support a number of different load commands. The load commands are
summarized in Table 11 and Table 12, and fully exhausted in Table 13.
Table 11. Commands for the DAC856x, DAC816x, and DAC756x
C2
(DB21)
0
0
0
0
1
1
1
1
C1
(DB20)
0
0
1
1
0
0
1
1
C0
(DB19)
0
1
0
1
0
1
0
1
Command
Write to input register n (Table 12)
Software LDAC, update DAC register n (Table 12)
Write to input register n (Table 12) and update all DAC registers
Write to input register n and update DAC register n (Table 12)
Set DAC power up/down mode
Software reset
Set LDAC registers
Enable/disable internal reference
Table 12. Address Select for the DAC856x, DAC816x, and DAC756x
A2
(DB18)
0
0
0
0
1
1
1
1
A1
(DB17)
0
0
1
1
0
0
1
1
A0
(DB16)
0
1
0
1
0
1
0
1
Channel (n)
DAC-A
DAC-B
Gain (only use with command 000)
Reserved
Reserved
Reserved
Reserved
DAC-A and DAC-B
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