DAC8562SDSCT Datasheet, PDF (23/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

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DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS: DAC at AV_DD = 2.7 V (continued)
At T_A = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
POWER-DOWN CURRENT
vs TEMPERATURE
3.0
DAC OUTPUT VOLTAGE
vs LOAD CURRENT
4
Typical channel shown
2.5
3
2.0
2
1.5
Full scale
Mid scale
Zero scale
1.0
1
0.5
0.0
−40 −25 −10 5
20 35 50 65 80 95 110 125
Temperature (°C)
G073
Figure 73.
0
−1
−20 −15 −10
−5 0
5
I_LOAD (mA)
Figure 74.
10 15 20
FULL-SCALE SETTLING TIME:
RISING EDGE
LDAC Trigger (5 V/div)
Large Signal V_OUT (1 V/div)
FULL-SCALE SETTLING TIME:
FALLING EDGE
LDAC Trigger (5 V/div)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
Time (5 μs/div)
Figure 75.
From Code: 0h
To Code: FFFFh
HALF-SCALE SETTLING TIME:
RISING EDGE
LDAC Trigger (5 V/div)
Large Signal V_OUT (1 V/div)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
Large Signal V_OUT (1 V/div)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
Time (5 μs/div)
Figure 76.
From Code: FFFFh
To Code: 0h
HALF-SCALE SETTLING TIME:
FALLING EDGE
LDAC Trigger (5 V/div)
Large Signal V_OUT (1 V/div)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
Time (5 μs/div)
Figure 77.
From Code: 4000h
To Code: C000h
Time (5 μs/div)
Figure 78.
From Code: C000h
To Code: 4000h
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