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| DAC8562SDSCT Datasheet, PDF (4/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON | |||
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DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D â AUGUST 2010 â REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
At AVDD = 2.7 V to 5.5 V and TA = â40°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
STATIC PERFORMANCE(1)
Resolution
DAC856x
Relative accuracy
Using line passing through codes 512 and 65,024
Differential nonlinearity 16-bit monotonic
Resolution
DAC816x
Relative accuracy
Using line passing through codes 128 and 16,256
Differential nonlinearity 14-bit monotonic
Resolution
DAC756x
Relative accuracy
Using line passing through codes 32 and 4,064
Offset error
Differential nonlinearity 12-bit monotonic
Extrapolated from two-point line(1), unloaded
Offset error drift
Full-scale error
DAC register loaded with all 1s
Zero-code error
DAC register loaded with all 0s
Zero-code error drift
Gain error
Extrapolated from two-point line(1), unloaded
Gain temperature coefficient
OUTPUT CHARACTERISTICS(2)
Output voltage range
Output voltage settling time(3)
Slew rate
Capacitive load stability
Code-change glitch impulse
Digital feedthrough
Power-on glitch impulse
Channel-to-channel dc crosstalk
DC output impedance
Short-circuit current
Power-up time, including settling time
AC PERFORMANCE(2)
DAC output noise density
DAC output noise
LOGIC INPUTS(2)
Input pin Leakage current
Logic input LOW voltage VINL
DACs unloaded
RL = 1 Mâ¦
Measured between 20% - 80% of a full-scale transition
RL = â
RL = 2 kâ¦
1-LSB change around major carry
SCLK toggling, SYNC high
RL = 2 kâ¦, CL = 470 pF, AVDD = 5.5 V
Full-scale swing on adjacent channel,
External reference
Full-scale swing on adjacent channel,
Internal reference
At mid-scale input
DAC outputs at full-scale, DAC outputs shorted to
GND
Coming out of power-down mode
TA = 25°C, at mid-scale input, fOUT = 1 kHz
TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz
Logic input HIGH voltage VINH
Pin capacitance
(1) 16-bit: codes 512 and 65,024; 14-bit: codes 128 and 16,256; 12-bit: codes 32 and 4,064
(2) Specified by design or characterization
(3) Transition time between 1/4 scale and 3/4 scale including settling to within ±0.024% FSR
MIN
16
14
12
0
â1
0
0.7 Ã
AVDD
TYP
±4
±0.2
±1
±0.1
±0.3
±0.05
±1
±2
±0.03
1
±2
±0.01
±1
7
10
0.75
1
3
0.1
0.1
40
5
15
5
40
50
90
2.6
±0.1
www.ti.com
MAX UNIT
±12
±1
±3
±0.5
±0.75
±0.25
±4
±0.2
4
±0.15
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
µV/°C
% FSR
mV
µV/°C
% FSR
ppm
FSR/°C
AVDD
V
µs
V/µs
nF
nV-s
nV-s
mV
µV
Ω
mA
µs
nV/âHz
µVPP
1
µA
0.8
V
AVDD
V
3
pF
4
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Copyright © 2010â2012, Texas Instruments Incorporated
Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563
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