DAC8562SDSCT Datasheet, PDF (30/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
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Power-On Reset (POR) Levels
When the device powers up, a POR circuit sets the device in default mode as shown in Table 6. The POR circuit
requires specific AV_DD levels, as indicated in Figure 91, to ensure discharging of internal capacitors and to reset
the device on power up. In order to ensure a power-on reset, AV_DD must be below 0.7 V for at least 1 ms. When
AV_DD drops below 2.2 V but remains above 0.7 V (shown as the undefined region), the device may or may not
reset under all specified temperature and power-supply conditions. In this case, TI recommends a power-on
reset. When AV_DD remains above 2.2 V, a power-on reset does not occur.
AV_DD (V)
5.50
No Power-On Reset
Specified Supply
Voltage Range
2.70
2.20
Undefined
0.70
Power-On Reset
0.00
Figure 91. Relevant Voltage Levels for POR Circuit
CLR FUNCTIONALITY
The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 7.
When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output
voltages accordingly. The part exits clear mode on the 24^th falling edge of the next write to the part. If the CLR
pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and
changes the input and DAC registers immediately according to Table 7.
Table 7. Clear Mode Reset Values
DEVICE
DAC8562, DAC8162, DAC7562
DAC8563, DAC8163, DAC7563
DAC Output Entering Clear Mode
Zero-scale
Mid-scale
30
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