DAC8562SDSCT Datasheet, PDF (6/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
PIN CONFIGURATIONS
DGS
(Top View)
DSC
(Top View)
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V_OUTA
1
V_OUTB
2
GND
3
LDAC
4
CLR
5
10
V_REFIN/V_REFOUT
V_OUTA 1
9
AV_DD
V_OUTB 2
8
D_IN
GND 3
7
SCLK
6
SYNC
LDAC ⁴
CLR ⁵
Thermal Pad⁽¹⁾
MSOP Package
SON Package
(1) It is recommended to connect the thermal pad to the ground plane for better thermal dissipation.
10 V_REFIN/V_REFOUT
9 AV_DD
8 D_IN
7 SCLK
6 _SYNC
PIN
NAME
AV_DD
CLR
D_IN
GND
LDAC
SCLK
SYNC
V_OUTA
V_OUTB
V_REFIN / V_REFOUT
Table 2. PIN DESCRIPTIONS
DESCRIPTION
NO.
9
Power-supply input, 2.7 V to 5.5 V
Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale
5
(DACxx62) or mid-scale (DACxx63) is loaded to all input and DAC registers. This sets the DAC output
voltages accordingly. The part exits clear code mode on the 24^th falling edge of the next write to the part. If
CLR is activated during a write sequence, the write is aborted.
8
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock
input. Schmitt-trigger logic input
3
Ground reference point for all circuitry on the device
In synchronous mode, data are updated with the falling edge of the 24^th SCLK cycle, which follows a falling
edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to
GND permanently or asserted and held low before sending commands to the device.
4
In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous
DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to
desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output
registers.
7
Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input
Level-triggered control input (active-low). This input is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock
6
edges. The DAC output updates following the 24^th clock falling edge. If SYNC is taken high before the 23^rd
clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the
DAC756x/DAC816x/DAC856x. Schmitt-trigger logic input
1
Analog output voltage from DAC-A
2
Analog output voltage from DAC-B
10 Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.
6
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