DAC8562SDSCT Datasheet, PDF (31/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

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DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
SERIAL INTERFACE
The DAC756x, DAC816x, and DAC856x have a 3-wire serial interface (SYNC, SCLK, and D_IN; see the Pin
Descriptions) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the
Serial Write Operation timing diagram (Figure 1) for an example of a typical write sequence.
The DAC756x, DAC816x, or DAC856x input shift register is 24-bits wide, consisting of two don’t care bits (DB23
to DB22), three command bits (DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to
DB0). The 16 data bits comprise the 16-, 14-, or 12-bit input code. All 24 bits of data are loaded into the DAC
under the control of the serial clock input, SCLK. DB23 (MSB) is the first bit that is loaded into the DAC shift
register. It is followed by the rest of the 24-bit word pattern, left-aligned. This configuration means that the first 24
bits of data are latched into the shift register, and any further clocking of data is ignored. When the DAC registers
are being written to, the DAC756x, DAC816x, and DAC856x receive all 24 bits of data, ignore DB23 and DB22,
and decode the next three bits (DB21 to DB19) in order to determine the DAC operating/control mode (see
Table 8 through Table 10). Bits DB18 to DB16 are used to address DAC channels. The next 16/14/12 bits of
data that follow are decoded by the DAC to determine the equivalent analog output. For more details on these
and other commands (such as write to LDAC register, power down DACs, etc.), see their respective sections.
The data format is straight binary, with all 0s corresponding to 0-V output and all 1s corresponding to full-scale
output. For all documentation purposes, the data format and representation used here is a true 16-bit pattern
(that is, FFFFh data word for full scale) that the DAC756x, DAC816x, and DAC856x require.
The write sequence begins by bringing the SYNC line low. Data from the D_IN line are clocked into the 24-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the
DAC756x, DAC816x, and DAC856x compatible with high-speed DSPs. On the 24^th falling edge of the serial
clock, the last data bit is clocked into the shift register and the shift register locks. Further clocking does not
change the shift register data.
After receiving the 24^th falling clock edge, the DAC756x, DAC816x, and DAC856x decode the three command
bits and three address bits and 16/14/12 data bits to perform the required function, without waiting for a SYNC
rising edge. After the 24^th falling edge of SCLK is received, the SYNC line may be kept low or brought high. In
either case, the minimum delay time from the 24^th falling SCLK edge to the next falling SYNC edge must be met
in order to begin the next cycle properly; see the Serial Write Operation timing diagram (Figure 1).
A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs.
A new write sequence starts at the next falling edge of SYNC. To assure the lowest power consumption of the
device, care should be taken that the levels are as close to each rail as possible.
SYNC Interrupt
In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed
DAC register updates on the 24^th falling edge. However, if SYNC is brought high before the 23^rd falling edge, it
acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither
an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as
shown in Figure 92).
24th Falling Edge
CLK
24th Falling Edge
SYNC
D_IN
DB23
DB0
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the Falling Edge
DB23
DB0
Valid Write Sequence:
Output/Mode Updates on the Falling Edge
Figure 92. SYNC Interrupt Facility
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