DAC8562SDSCT Datasheet, PDF (36/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
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SOFTWARE RESET FUNCTION
The DAC756x, DAC816x, and DAC856x contain a software reset feature. The software reset function uses
command 101. The software reset command contains two reset modes which are software-programmable by
setting bit DB0 in the shift register. Table 13 and/or Table 19 and Table 20 show the available software reset
commands.
Table 19. Software Reset Command Structure
Command
Address
Data
X X 1 0 1 X X X X X X X X X X X X X X X X X X RST
DB23
DB0
RST (DB0)
0
1
Table 20. Software Reset
Registers Reset to Default Values
DAC registers
Input registers
DAC registers
Input registers
LDAC registers
Power-down registers
Internal reference register
Gain registers
LDAC FUNCTIONALITY
The DAC756x, DAC816x, and DAC856x offer both a software and hardware simultaneous update and control
function. The DAC double-buffered architecture has been designed so that new data can be entered for each
DAC without disturbing the analog outputs.
DAC756x, DAC816x, and DAC856x data updates can be performed either in synchronous or in asynchronous
mode.
In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC
updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values
and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. Data buffers of all
channels must be loaded with desired data before an LDAC falling edge. After a high-to-low LDAC transition, all
DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a
data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered.
LDAC must be returned high before the next serial command is initiated.
In synchronous mode, data are updated with the falling edge of the 24^th SCLK cycle, which follows a falling edge
of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND
permanently or asserted and held low before sending commands to the device.
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