DAC8562SDSCT Datasheet, PDF (37/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

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DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The
LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be
updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 2-bit word
(DB1 and DB0) using command bits C2, C1, and C0 (see Table 13 or Table 21). The default value for each bit,
and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the
LDAC pin is internally tied low for that particular DAC channel) and this DAC channel updates synchronously
after the falling edge of the 24^th SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is
controlled by the LDAC pin.
The combination of software and hardware simultaneous update functions is particularly useful in applications
when updating a DAC channel, while keeping the other channel unaffected; see Table 13 or Table 21 and
Table 22 for more information.
Table 21. LDAC Register Command Structure
Command
Address
Data
X X 1 1 0 X X X X X X X X X X X X X X X X X DAC-B DAC-A
DB23
DB0
DB1/DB0
DB0
DB1
Table 22. DAC-n Selection for LDAC Register Command
Value
0
1
0
1
LDAC Pin Functionality
DAC-A uses LDAC pin
DAC-A operates in synchronous mode
DAC-B uses LDAC pin
DAC-B operates in synchronous mode
INTERNAL REFERENCE ENABLE REGISTER
The internal reference in the DAC756x, DAC816x, and DAC856x is disabled by default for debugging, evaluation
purposes, or when using an external reference. The internal reference can be powered up and powered down
using a serial command that requires a 24-bit write sequence, as shown in Table 23 and Table 24. The internal
reference is forced to a powered down state while both DAC channels are powered down, and is only enabled if
any DAC channel is in normal mode of operation in addition to using the command in Table 23. During the time
that the internal reference is disabled, the DAC functions normally using an external reference. At this point, the
internal reference is disconnected from the V_REFIN/V_REFOUT pin (Hi-Z output).
Enabling Internal Reference
To enable the internal reference, write the 24-bit serial command shown in Table 23. When performing a power
cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal
reference is powered down until a valid write sequence is applied to power up the internal reference. However,
the internal reference is forced to a disabled state while both DAC channels are powered down, and remains
disabled until either DAC channel is returned to the normal mode of operation. See DAC Power-Down
Commands for more information on DAC channel modes of operation.
Table 23. Write Sequence for Enabling Internal Reference
Command
Address
Data
XX1 1 1XXXXXXXXXXXXXXXXXX1
DB23
DB0
Disabling Internal Reference
To disable the internal reference, write the 24-bit serial command shown in Table 24. When performing a power
cycle to reset the device, the internal reference is disabled (default mode).
Table 24. Write Sequence for Disabling Internal Reference
Command
Address
Data
XX1 1 1XXXXXXXXXXXXXXXXXX0
DB23
DB0
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