DAC8562SDSCT Datasheet, PDF (42/58 Pages) Texas Instruments – DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON

DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
MICROPROCESSOR INTERFACING
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DAC756x/DAC816x/DAC856x to an MSP430 USI Interface
Figure 98 shows a serial interface between the DAC756x, DAC816x, or DAC856x and a typical MSP430 USI port
such as the one found on the MSP430F2013. The port is configured in SPI master mode by setting bits 3, 5, 6,
and 7 in USICTL0. The USI counter interrupt is set in USICTL1 to provide an efficient means of SPI
communication with minimal software overhead. The serial clock polarity, source, and speed are controlled by
settings in the USI clock control register (USICKCTL). The SYNC signal is derived from a bit-programmable pin
on port 1; in this case, port line P1.4 is used. When data are to be transmitted to the DAC756x, DAC816x, or
DAC856x, P1.4 is taken low. The USI transmits data in 8-bit bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P1.4 is left low after the first eight bits are transmitted; then, a
second write cycle is initiated to transmit the second byte of data. P1.4 is taken high following the completion of
the third write cycle.
MSP430F2013
P1.4/GPIO
P1.5/SCLK
P1.6/SDO
DAC
SYNC
SCLK
D_IN
NOTE: Additional pins omitted for clarity.
Figure 98. DAC756x/DAC816x/DAC856x to MSP430 Interface
DAC756x/DAC816x/DAC856x to a TMS320 McBSP Interface
Figure 99 shows an interface between the DAC756x, DAC816x, or DAC856x and any TMS320 series DSP from
Texas Instruments with a multi-channel buffered serial port (McBSP). Serial data are shifted out on the rising
edge of the serial clock and are clocked into the DAC756x, DAC816x, or DAC856x on the falling edge of the
SCLK signal.
TMS320F28062
MFSxA
MCLKxA
MDxA
DAC
SYNC
SCLK
D_IN
NOTE: Additional pins omitted for clarity.
Figure 99. DAC756x/DAC816x/DAC856x to TMS320 McBSP Interface
DAC756x/DAC816x/DAC856x to an OMAP-L1x Processor
Figure 100 shows a serial interface between the DAC756x/DAC816x/DAC856x and the OMAP-L138. The
transmit clock CLKx0 of the L138 drives SCLK of the DAC756x, DAC816x, or DAC856x, and the data transmit
(Dx0) output drives the serial data line of the DAC. The SYNC signal is derived from the frame sync transmit
(FSx0) line, similar to the TMS320 interface.
OMAP-L138
FSx0
CLKx0
Dx0
DAC
SYNC
SCLK
D_IN
NOTE: Additional pins omitted for clarity.
Figure 100. DAC756x/DAC816x/DAC856x to OMAP-L1x Processor
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