DRV2604L Datasheet, PDF (56/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
www.ti.com
8.6.24 RAM-Address Upper Byte (Address: 0xFD)
Figure 56. RAM-Address Upper-Byte Register
7
6
5
4
3
2
1
0
RAM_ADDR_UB[7:0]
R/W-0
Table 26. RAM-Address Upper-Byte Register Field Descriptions
BIT FIELD
7-0 RAM_ADDR_UB[7:0]
TYPE
R/W
DEFAULT
0
DESCRIPTION
The content of this bit is the upper byte for the waveform RAM Address entry.
8.6.25 RAM-Address Lower Byte (Address: 0xFE)
Figure 57. RAM-Address Lower Byte Register
7
6
5
4
3
2
1
0
RAM_ADDR_LB[7:0]
R/W-0
Table 27. RAM Address Lower Byte Register Field Descriptions
BIT FIELD
7-0 RAM_ADDR_LB[7:0]
TYPE
R/W
DEFAULT
0
DESCRIPTION
The content of this bit is the lower byte for the waveform RAM address entry.
8.6.26 RAM Data Byte (Address: 0xFF)
Figure 58. RAM-Data Byte Register
7
6
5
4
3
2
1
0
RAM_DATA[7:0]
R/W-0
BIT FIELD
7-0 RAM_DATA[7:0]
Table 28. RAM-Data Byte Register Field Descriptions
TYPE
R/W
DEFAULT
0
DESCRIPTION
Data entry to waveform RAM interface. The user can perform single-byte writes
or multi-byte writes to this register. The controller starts the write at the address
(RAM_ADDR_UB:RAM_ADDR_LB). For both single-byte and multi-byte writes,
the controller automatically increments the RAM address register for each byte
written to the RAM data register.
56
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