DRV2604L Datasheet, PDF (20/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
www.ti.com
8.4 Device Functional Modes
8.4.1 Power States
The DRV2604L device has three different power states which allow for different power-consumption levels and
functions. Figure 16 shows the transition in to and out of each state.
EN = 0
Shutdown
EN = 1
STANDBY = 0
Standby
EN = 0
Active
STANDBY = 1
DEV_RESET = 1
Figure 16. Power-State Transition Diagram
8.4.1.1 Operation With V_DD < 2 V (Minimum V_DD)
Operating the device with a V_DD value below 2 V is not recommended.
8.4.1.2 Operation With V_DD > 5.5 V (Absolute Maximum V_DD)
The DRV2604L device is designed to operate at up to 5.2 V, with an absolute maximum voltage of 5.5 V. If
exposed to voltages above 5.5 V, the device can suffer permanent damage.
8.4.1.3 Operation With EN Control
The EN pin of the DRV2604L device gates the active operation. When the EN pin is logic high, the DRV2604L
device is active. When the EN pin is logic low, the device enters the shutdown state, which is the lowest power
state of the device. The device registers are not reset. The EN pin operation is particularly useful for constant-
source PWM and analog input modes to maintain compatibility with non-I²C device signaling. The EN pin must
be high to write I²C device registers. However, if the EN pin is low the DRV2604L device can still acknowledge
(ACK) during an I²C transaction, however, no read or write is possible. To completely reset the device to the
powerup state, set the DEV_RESET bit in register 0x01.
8.4.1.4 Operation With STANDBY Control
The STANDBY bit in register 0x01 forces the device in an out of the standby state. The STANDBY bit is asserted
by default. When the STANDBY bit is asserted, the DRV2604L device goes into a low-power state. In the
standby state the device retains register values and the ability to have I²C communication. The properties of the
standby state also feature a fast turn, wake up, and play, on-time. Asserting the STANDBY bit has an immediate
effect. For example, if a waveform is played, it immediately stops when the STANDBY bit is asserted.
Clear the STANDBY bit to exit the standby state (and go to the ready state).
8.4.1.5 Operation With DEV_RESET Control
The DEV_RESET bit in register 0x01 performs the equivalent of power cycling the device. Any playback
operations are immediately interrupted, and all registers are reset to the default values. The Dev_Reset bit
automatically-clears after the reset operation is complete.
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