DRV2604L Datasheet, PDF (54/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
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8.6.20 Control5 (Address: 0x1F)
Figure 52. Control5 Register
7
6
AUTO_OL_CNT[1:0]
R/W-1
R/W-0
BIT FIELD
7-6 AUTO_OL_CNT[1:0]
5
LRA_AUTO_OPEN_LOOP
4
PLAYBACK_INTERVAL
3-2 BLANKING_TIME[3:2]
1-0 IDISS_TIME[3:2]
5
LRA_AUTO_O
PEN_LOOP
R/W-0
4
PLAYBACK_IN
TERVAL
R/W-0
3
2
BLANKING_TIME[3:2]
RW-0
RW-0
Table 22. Control5 Register Field Descriptions
1
0
IDISS_TIME[3:2]
RW-0
TYPE
R/W
R/W
R/W
R/W
R/W
DEFAULT
2
0
0
0
0
DESCRIPTION
This bit selects number of cycles required to attempt synchronization before
transitioning to open loop when the LRA_AUTO_OPEN_LOOP bit is asserted,
0: 3 attempts
1: 4 attempts
2: 5 attempts
3: 6 attempts
This bit selects the automatic transition to open-loop drive when a back-EMF
signal is not detected (LRA only).
0: Never transitions to open loop
1: Automatically transitions to open loop
This bit selects the memory playback interval.
0: 5 ms
1: 1 ms
This bit sets the MSB for the BLANKING_TIME[3:0]. See the
BLANKING_TIME[3:0] bit in the Control2 (Address: 0x1C) section for details.
Advanced use only.
This bit sets the MSB for IDISS_TIME[3:0]. See the IDISS_TIME[1:0] bit in the
Control2 (Address: 0x1C) section for details. Advanced use only.
8.6.21 LRA Open Loop Period (Address: 0x20)
Figure 53. LRA Open Loop Period Register
7
6
5
4
3
2
1
0
Reserved
OL_LRA_PERIOD[6:0]
R/W-0
BIT
FIELD
7-0 OL_LRA_PERIOD[6:0]
Table 23. LRA Open Loop Period Register Field Descriptions
TYPE
R/W
DEFAULT
0
DESCRIPTION
This bit sets the period to be used for driving an LRA when open-loop mode is
selected.
LRA open-loop period (µs) = OL_LRA_PERIOD[6:0] × 98.46 µs
8.6.22 V_(BAT) Voltage Monitor (Address: 0x21)
Figure 54. V_(BAT) Voltage-Monitor Register
7
6
5
4
3
2
1
0
VBAT[7:0]
R/W-0
54
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