DRV2604L Datasheet, PDF (26/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
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Programming (continued)
8.5.3.2 Single-Byte and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte R/W operations for all registers.
During multiple-byte read operations, the DRV2604L device responds with data one byte at a time and beginning
at the signed register. The device responds as long as the master device continues to respond with
acknowledges.
The DRV2604L supports sequential I²C addressing. For write transactions, a sequential I²C write transaction has
taken place if a register is issued followed by data for that register as well as the remaining registers that follow.
For I²C sequential-write transactions, the register issued then serves as the starting point and the amount of data
transmitted subsequently before a stop or start is transmitted determines how many registers are written.
8.5.3.3 Single-Byte Write
As shown in Figure 20, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I²C device address and the read-write bit. The read-write bit determines the direction of
the data transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I²C
device address and the read-write bit, the DRV2604L responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the DRV2604L internal-memory address that is accessed. After
receiving the register byte, the device responds again with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.
Acknowledge
Acknowledge
Acknowledge
A6 A5 A4 A3 A2 A1 A0 W ACK A7 A6 A5 A4 A3 A2 A0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
condition
I²C device address
and R/W bit
Subaddress
Figure 20. Single-Byte Write Transfer
Data byte
Stop
condition
8.5.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DRV2604L device as shown in Figure 21. After receiving each data
byte, the DRV2604L device responds with an acknowledge bit.
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A1 A0
A1 A0 W ACK A7 A6
A1 A0 ACK D7 D6
D1 D0 ACK D7
D0 ACK D7
D0 ACK
Start
condition
2
I C device address
and R/W bit
Subaddress
First data byte
Other data bytes
Last data byte
Stop
condition
Figure 21. Multiple-Byte Write Transfer
8.5.3.5 Single-Byte Read
Figure 22 shows that a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I²C device address and the read-write bit. For the data-read transfer, both a write followed by a
read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be
read. As a result, the read-write bit is set to 0.
After receiving the DRV2604L address and the read-write bit, the DRV2604L device responds with an
acknowledge bit. The master then sends the internal memory address byte, after which the device issues an
acknowledge bit. The master device transmits another start condition followed by the DRV2604L address and the
read-write bit again. This time, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2604L
device transmits the data byte from the memory address that is read. After receiving the data byte, the master
device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
See the note in the General I²C Operation section.
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