DRV2604L Datasheet, PDF (38/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
8.6 Register Map
REG
NO.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0xFD
0xFE
0xFF
DEFAULT
0xC0
0x40
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x3E
0x9B
0x0C
0x6F
0x36
0x93
0xF5
0x80
0x20
0x80
0x33
0x00
0x00
0x00
0x00
0x00
BIT 7
DEV_RESET
WAIT1
WAIT2
WAIT3
WAIT4
WAIT5
WAIT6
WAIT7
WAIT8
BIT 6
DEVICE_ID[2:0]
STANDBY
Reserved
N_ERM_LRA
STARTUP_BOOST
Reserved
BIDIR_INPUT
BRAKE_STABILIZER
NG_THRESH[1:0]
ZC_DET_TIME[1:0]
AUTO_OL_CNT[1:0]
Reserved
www.ti.com
Table 2. Register Map Overview
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
DIAG_RESULT
Reserved
OVER_TEMP
OC_DETECT
Reserved
MODE[2:0]
RTP_INPUT[7:0]
HI_Z
Reserved
WAV_FRM_SEQ1[6:0]
WAV_FRM_SEQ2[6:0]
WAV_FRM_SEQ3[6:0]
WAV_FRM_SEQ4[6:0]
WAV_FRM_SEQ5[6:0]
WAV_FRM_SEQ6[6:0]
WAV_FRM_SEQ7[6:0]
WAV_FRM_SEQ8[6:0]
Reserved
GO
ODT[7:0]
SPT[7:0]
SNT[7:0]
BRT[7:0]
RATED_VOLTAGE[7:0]
OD_CLAMP[7:0]
A_CAL_COMP[7:0]
A_CAL_BEMF[7:0]
FB_BRAKE_FACTOR[2:0]
LOOP_GAIN[1:0]
BEMF_GAIN[1:0]
AC_COUPLE
DRIVE_TIME[4:0]
SAMPLE_TIME[1:0]
BLANKING_TIME[1:0]
IDISS_TIME[1:0]
ERM_OPEN_LOOP
SUPPLY_COMP_DIS
DATA_FORMAT_RTP LRA_DRIVE_MODE
N_PWM_ANALOG
LRA_OPEN_LOOP
AUTO_CAL_TIME[1:0]
Reserved
OTP_STATUS
Reserved
OTP_PROGRAM
LRA_AUTO_OPEN_LOOP PLAYBACK_INTERVAL
BLANKING_TIME[3:2]
IDISS_TIME[3:2]
OL_LRA_PERIOD[6:0]
VBAT[7:0]
LRA_PERIOD[7:0]
RAM_ADDR_UB[7:0]
RAM_ADDR_LB[7:0]
RAM_DATA[7:0]
38
Submit Documentation Feedback
Product Folder Links: DRV2604L
Copyright © 2014–2015, Texas Instruments Incorporated