DRV2604L Datasheet, PDF (27/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

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Programming (continued)
DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A6 A5
A1 A0 W ACK A7 A6
A1 A0 ACK
A6 A5
A0 R ACK D7
D0 ACK
Start
Condition
2
I C device address and
R/W bit
Subaddress
Repeat start
2
I C device address and
condition
R/W bit
Figure 22. Single-Byte Read Transfer
Data Byte
Stop
Condition
8.5.3.6 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the DRV2604L device to the master device as shown in Figure 23. With the exception of the
last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Acknowledge
Acknowledge
Acknowledge Acknowledge Acknowledge Acknowledge
A6
A0 W ACK A7 A6
A1 A0 ACK
A6 A5 A0 R ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
Start _I²_{C device address}
condition _{and R/W bit}
Subaddress
Repeat start
2
I C device address
condition
and R/W bit
First data byte Other data byte Last data byte
Figure 23. Multiple-Byte Read Transfer
Stop
condition
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