DRV2604L Datasheet, PDF (52/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
www.ti.com
8.6.18 Control3 (Address: 0x1D)
Figure 50. Control3 Register
7
6
NG_THRESH[1:0]
R/W-1
R/W-0
BIT
FIELD
7-6 NG_THRESH[1:0]
5 ERM_OPEN_LOOP
4 SUPPLY_COMP_DIS
3 DATA_FORMAT_RTP
2 LRA_DRIVE_MODE
1 N_PWM_ANALOG
0 LRA_OPEN_LOOP
5
ERM_OPEN_L
OOP
R/W-0
4
SUPPLY_COM
P_DIS
R/W-0
3
DATA_FORMA
T_RTP
R/W-0
2
LRA_DRIVE_M
ODE
R/W-0
1
N_PWM_ANAL
OG
R/W-0
0
LRA_OPEN_L
OOP
R/W-0
Table 20. Control3 Register Field Descriptions
TYPE DEFAULT
R/W 2
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DESCRIPTION
This bit is the noise-gate threshold for PWM and analog inputs.
0: Disabled
1: 2%
2: 4% (Default)
3: 8%
This bit selects mode of operation while in ERM mode. Closed-loop operation is
usually desired for because of automatic overdrive and braking properties.
However, many existing waveform libraries were designed for open-loop
operation, therefore open-loop operation can be required for compatibility.
0: Closed Loop
1: Open Loop
This bit disables supply compensation. The DRV2604L device generally
provides constant drive output over variation in the power supply input (V_DD). In
some systems, supply compensation can have already been implemented
upstream, therefore disabling the DRV2604L supply compensation can be
useful.
0: Supply compensation enabled
1: Supply compensation disabled
This bit selects the input data interpretation for RTP (Real-Time Playback)
mode.
0: Signed
1: Unsigned
This bit selects the drive mode for the LRA algorithm. This bit determines how
often the drive amplitude is updated. Updating once per cycle provides a
symmetrical output signal, while updating twice per cycle provides more precise
control.
0: Once per cycle
1: Twice per cycle
This bit selects the input mode for the IN/TRIG pin when MODE[2:0] = 3. In
PWM input mode, the duty cycle of the input signal determines the amplitude of
the waveform. In analog input mode, the amplitude of the input determines the
amplitude of the waveform.
0: PWM Input
1: Analog Input
This bit selects an open-loop drive option for LRA Mode. When asserted, the
playback engine drives the LRA at the selected frequency independently of the
resonance frequency. In PWM input mode, the playback engine recovers the
LRA commutation frequency from the PWM input, dividing the frequency by
128. Therefore the PWM input frequency must be equal to 128 times the
resonant frequency of the LRA.
In RTP, RAM mode, the frequency is set by the OL_LRA_PERIOD[6:0] bit.
Open-loop mode is not supported if analog input mode is selected.
0: Auto-resonance mode
1: LRA open-loop mode
52
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