DRV2604L Datasheet, PDF (55/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

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DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
BIT FIELD
7-0 VBAT[7:0]
Table 24. V_(BAT) Voltage-Monitor Register Field Descriptions
TYPE DEFAULT DESCRIPTION
R/W 0
This bit provides a real-time reading of the supply voltage at the V_DD pin. The
device must be actively sending a waveform to take a reading.
V_DD (V) = VBAT[7:0] × 5.6V / 255
8.6.23 LRA Resonance Period (Address: 0x22)
Figure 55. LRA Resonance-Period Register
7
6
5
4
3
2
1
0
LRA_PERIOD[7:0]
R/W-0
BIT FIELD
7-0 LRA_PERIOD[7:0]
Table 25. LRA Resonance-Period Register Field Descriptions
TYPE
R/W
DEFAULT
0
DESCRIPTION
This bit reports the measurement of the LRA resonance period. The device must
be actively sending a waveform to take a reading.
LRA period (us) = LRA_Period[7:0] × 98.46 µs
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