DRV2604L Datasheet, PDF (53/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

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DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
8.6.19 Control4 (Address: 0x1E)
Figure 51. Control4 Register
7
6
ZC_DET_TIME[ ZC_DET_TIME[
1]
0]
R/W-0
R/W-0
5
4
AUTO_CAL_TIME[1:0]
3
Reserved
2
OTP_STATUS
R/W-1
R/W-0
R-0
Table 21. Control4 Register Field Descriptions
1
Reserved
0
OTP_PROGRA
M
R/W-0
BIT FIELD
7-6 ZC_DET_TIME[1:0]
5-4 AUTO_CAL_TIME[1:0]
3
Reserved
2
OTP_STATUS
1
Reserved
0
OTP_PROGRAM
TYPE
R/W
R/W
DEFAULT
0
2
DESCRIPTION
This bit sets the minimum length of time devoted for detecting a zero crossing
(advanced use only).
0: 100 µs
1: 200 µs
2: 300 µs
3: 390 µs
This bit sets the length of the auto calibration time. The AUTO_CAL_TIME[1:0]
bit should be enough time for the motor acceleration to settle when driven at the
RATED_VOLTAGE[7:0] value.
0: 150 ms (minimum), 350 ms (maximum)
1: 250 ms (minimum), 450 ms (maximum)
2: 500 ms (minimum), 700 ms (maximum)
3: 1000 ms (minimum), 1200 ms (maximum)
R
0
OTP Memory status
0: OTP Memory has not been programmed
1: OTP Memory has been programmed
R/W
0
This bit launches the programming process for one-time programmable (OTP)
memory which programs the contents of register 0x16 through 0x1A into
nonvolatile memory. This process can only be executed one time per device.
See the Programming On-Chip OTP Memory section for details.
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