DRV2604L Datasheet, PDF (48/73 Pages) Texas Instruments – DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

DRV2604L
SLOS866D – MAY 2014 – REVISED JUNE 2015
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8.6.16 Control1 (Address: 0x1B)
Figure 48. Control1 Register
7
STARTUP_BO
OST
R/W-1
6
Reserved
BIT FIELD
7 STARTUP_BOOST
6 Reserved
5 AC_COUPLE
4-0 DRIVE_TIME[4:0]
5
4
3
2
1
0
AC_COUPLE
DRIVE_TIME[4:0]
R/W-0
R/W-1
R/W-0
R/W-0
Table 18. Control1 Register Field Descriptions
R/W-1
R/W-1
TYPE
R/W
DEFAULT
1
DESCRIPTION
This bit applies higher loop gain during overdrive to enhance actuator transient
response.
R/W
0
R/W
0x13
This bit applies a 0.9-V common mode voltage to the IN/TRIG pin when an AC-
coupling capacitor is used. This bit is only useful for analog input mode. This bit
should not be asserted for PWM mode or external trigger mode.
0: Common-mode drive disabled for DC-coupling or digital inputs modes
1: Common-mode drive enabled for AC coupling
LRA Mode: Sets initial guess for LRA drive-time in LRA mode. Drive time is
automatically adjusted for optimum drive in real time; however, this register
should be optimized for the approximate LRA frequency. If the bit is set too low,
it can affect the actuator startup time. If the bit is set too high, it can cause
instability.
Optimum drive time (ms) ≈ 0.5 × LRA Period
Drive time (ms) = DRIVE_TIME[4:0] × 0.1 ms + 0.5 ms
ERM Mode: Sets the sample rate for the back-EMF detection. Lower drive times
cause higher peak-to-average ratios in the output signal, requiring more supply
headroom. Higher drive times cause the feedback to react at a slower rate.
Drive Time (ms) = DRIVE_TIME[4:0] × 0.2 ms + 1 ms
48
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