DS90UH926Q Datasheet, PDF (54/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
Revision
• March 7, 2012
— Deleted “DC Electrical Characteristics” PDB VDDIO = 1.71 to 1.89V
— Added under “SUPPLY CURRENT I_{DDZ, DDIOZ}, I_DDIOZMax = 10mA
— Added under “CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS” E_W Min = 0.3 UI AND E_H Min = 200 mV
— Added “INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)” under Functional Description section
— Updated "POWER DOWN (PDB) description under Functional Description from VDDIO to VDDIO = 3.0 to 3.6V or V_DD33
— Updated “FIGURE 22. Typical Connection Diagram”
• Aug 6, 2012
— Corrected TABLE 1: Configuration Select (MODE_SEL) #6 I2S Channel B (18–bit Mode) from L to H
— Corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33
— Added Recommended FRC settings table
— Added “When backward compatible mode = ON, set LFMODE = 0” under Functional Description. Reformatted TABLE 4 and
added clarification to notes. Added clarification to notes on TABLE 9 Serial Control Bus Registers, address 0x02[3:0]
(backwards compatible and LFMODE registers).
— Added “Note: Do not enable SSCG feature if PCLK source into the SER has an SSC clock already.” under Functional
Description, EMI REDUCTION FEATURES, Spread Spectrum Clock Generation (SSCG)
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