DS90UH926Q Datasheet, PDF (10/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
Symbol
Parameter
Conditions
Data Valid After OEN = H
t_ONS
SetupTime
Figure 7 (Note 8, Note 9)
VDDIO = 1.71 - 1.89V,
CL = 12pF
VDDIO = 3.0 – 3.6V,
CL = 12pF
Data Tri-State After OEN = L VDDIO = 1.71 - 1.89V,
SetupTime
t_ONH
Figure 7 (Note 8, Note 9)
CL = 12pF
VDDIO = 3.0 – 3.6V,
CL = 12pF
VDDIO = 1.71 - 1.89V,
Data Tri-State after OSS_ SEL _{CL = 12pF}
t_SES
= H, Setup Time
Figure 7 (Note 8, Note 9)
VDDIO = 3.0 – 3.6V,
CL = 12pF
t_SEH
VDDIO = 1.71 - 1.89V,
Data to Low after OSS_SEL = L _{CL = 12pF}
Setup Time
Figure 7 (Note 8, Note 9)
VDDIO = 3.0 – 3.6V,
CL = 12pF
BIST Mode
t_PASS
BIST PASS Valid Time
BISTEN = H
Figure 8 (Note 8, Note 9)
SSCG Mode
f_DEV
f_MOD
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
Figure 12
Tables 1, 2
(Note 8, Note 9)
Pin/Freq. Min
R[7:0], G
[7:0], B[7:0],
HS, VS, DE,
PCLK,
MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
Typ Max Units
50
ns
50
ns
50
ns
50
ns
5
ns
5
ns
5
ns
5
ns
PASS
800
ns
f = 85MHz,
SSCG = ON
±0.5
8
±2.5 %
100 kHz
Recommended Timing for the Serial Control Bus
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
f_SCL
SCL Clock Frequency
Standard Mode
Fast Mode
t_LOW
SCL Low Period
Standard Mode
Fast Mode
t_HIGH
SCL High Period
Standard Mode
Fast Mode
t_HD;STA
Hold time for a start or a
repeated start condition
Figure 9
Standard Mode
Fast Mode
t_SU:STA
Set Up time for a start or a
repeated start condition
Figure 9
Standard Mode
Fast Mode
t_HD;DAT
Data Hold Time
Figure 9
Standard Mode
Fast Mode
t_SU;DAT
Data Set Up Time
Figure 9
Standard Mode
Fast Mode
t_SU;STO
Set Up Time for STOP
Condition, Figure 9
Standard Mode
Fast Mode
t_BUF
Bus Free Time
Standard Mode
Between STOP and START,
Figure 9
Fast Mode
Min Typ Max Units
0
100 kHz
0
400 kHz
4.7
us
1.3
us
4.0
us
0.6
us
4.0
us
0.6
us
4.7
us
0.6
us
0
3.45 us
0
0.9
us
250
ns
100
ns
4.0
us
0.6
us
4.7
us
1.3
us
10
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