DS90UH926Q Datasheet, PDF (17/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
TABLE 1. SSCG Configuration
LFMODE = L (15 - 85 MHz)
SSCG Configuration (0x2C) LFMODE = L (15 - 85MHz)
Spread Spectrum Output
SSC[2]
SSC[1]
SSC[0]
Fdev (%)
L
L
L
±0.9
L
L
H
±1.2
L
H
L
±1.9
L
H
H
±2.5
H
L
L
±0.7
H
L
H
±1.3
H
H
L
±2.0
H
H
H
±2.5
Fmod (kHz)
PCLK / 2168
PCLK / 1300
TABLE 2. SSCG Configuration
LFMODE = H (5 - <15 MHz)
SSCG Configuration (0x2C) LFMODE = H (5 - <15 MHz)
Spread Spectrum Output
SSC[2]
SSC[1]
SSC[0]
Fdev (%)
L
L
L
±0.5
L
L
H
±1.3
L
H
L
±1.8
L
H
H
±2.5
H
L
L
±0.7
H
L
H
±1.2
H
H
L
±2.0
H
H
H
±2.5
Fmod (kHz)
PCLK / 628
PCLK / 388
Enhanced Progressive Turn-On (EPTO)
The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a different time. This
minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition it spreads the noise
spectrum out reducing overall EMI.
LVCMOS VDDIO Option
The deserializer parallel bus can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility. The 1.8 V levels will
offer a lower noise (EMI) and also a system power savings.
POWER DOWN (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the host or through
the V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power disable the link when the display is not needed (PDB = LOW).
When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO have reached final levels; no external components
are required. In the case of driven by the V_DDIO = 3.0V to 3.6V or V_DD33 directly, a 10 kohm resistor to the V_DDIO = 3.0V to 3.6V or
V_DD33 , and a >10uF capacitor to the ground are required (See Figure 22 Typical Connection Diagram).
STOP STREAM SLEEP
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the
embedded clock bits are not present. When the serial stream starts again, the deserializer will then lock to the incoming signal and
recover the data. Note – in STOP STREAM SLEEP, the Serial Control Bus Registers values are retained.
SERIAL LINK FAULT DETECT
The serial link fault detection is able to detect any of following seven (7) conditions
1) cable open
2) “+” to “-“ short
3) “+” short to GND
4) “-“ short to GND
5) “+” short to battery
6) “-“ short to battery
7) Cable is linked incorrectly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control Bus Register bit
0 of address 0x1C Table 9. The link errors can be monitored though Link Error Count of the Serial Control Bus Register bit [4:0] of
address 0x41 Table 9.
Copyright © 1999-2012, Texas Instruments Incorporated
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