DS90UH926Q Datasheet, PDF (53/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
POWER UP REQUIREMENTS AND PDB PIN
The VDDs (V₃₃ and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is
needed to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to
V_DDIO = 3.0V to 3.6V or V_DD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.
All inputs must not be driven until V_DD33 and V_DDIO has reached its steady state value.
TRANSMISSION MEDIA
The DS90UH925Q and DS90UH926Q chipset is intended to be used in a point-to-point configuration through a shielded twisted
pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect
(cable and connector) between the serializer and deserializer should have a differential impedance of 100 Ohms. The maximum
length of cable that can be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities,
power plane), the electrical environment (e.g. power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the appli-
cation environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye
opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define the acceptable data eye opening
width and eye opening height. A differential probe should be used to measure across the termination resistor at the CMLOUT+/-
pin Figure 2 .
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power feed to the device.
Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup,
feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power /
ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which
has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical.
External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate
the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to
100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the
power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power
or ground pins to an external bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body size reduces the
parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors,
usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance
between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power
and ground pins to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables
typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be
used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML lines to prevent coupling
from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohms are typically recommended for CML
interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the
receivers. The tightly coupled lines will also radiate less.
Information on the LLP style package is provided in TI Application Note: AN-1187.
CML INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI web site at:
www.ti.com/lvds
Copyright © 1999-2012, Texas Instruments Incorporated
53