DS90UH926Q Datasheet, PDF (51/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
Applications Information
DISPLAY APPLICATION
The DS90UH926Q, in conjunction with the DS90UH925Q, is intended for interface between a HDCP compliant host (graphics
processor) and a Display. It supports an 24-bit color depth (RGB888) and high definition (720p) digital video format. It allows to
receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three control bits (VS, HS and DE) and three I2S-
bus audio stream with an audio sampling rate up to 192 kHz. The included HDCP 1.3 compliant cipher block allows the
authentication of the DS90UH926Q, which decrypts both video and audio contents. The keys are pre-loaded by TI into Non-Volatile
Memory (NVM) for maximum security.
The deserializer is expected to be located close to its target device. The interconnect between the deserializer and the target device
is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to be in the 5 to 10 pF range.
Care should be taken on the PCLK output trace as this signal is edge sensitive and strobes the data. It is also assumed that the
fanout of the deserializer is up to three in the repeater mode. If additional loads need to be driven, a logic buffer or mux device is
recommended.
TYPICAL APPLICATION CONNECTION
Figure 22 shows a typical application of the DS90UH926Q deserializer for an 85 MHz 24-bit Color Display Application. inputs utilize
0.1 μF coupling capacitors to the line and the deserializer provides internal termination. Bypass capacitors are placed near the
power supply pins. At a minimum, seven 0.1 μF capacitors and two 4.7 μF capacitors should be used for local device bypassing.
Ferrite beads are placed on the power lines for effective noise suppression. Since the device in the Pin/STRAP mode, two 10 kΩ
pull-up resistors are used on the parallel output bus to select the desired device features.
The interface to the target display is with 3.3V LVCMOS levels, thus the V_DDIO pins are connected to the 3.3 V rail. A delay cap is
placed on the PDB signal to delay the enabling of the device until power is stable.
Copyright © 1999-2012, Texas Instruments Incorporated
51