DS90UH926Q Datasheet, PDF (26/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
BUILT IN SELF TEST (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the low- speed back
channel. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics.
BIST Configuration and Status
The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or configuration register
(Table 9) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or 33 MHz internal
Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC frequency (default 33 MHz or
25MHz) through the register bit. When LFMODE = 1, the pin based configuration defaults to external PCLK or 12.5MHz MHz internal
Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the Back Channel.
The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors.
The PASS output pin toggles to flag any payloads that are received with 1 to 35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset (new BIST test
or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were
detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. This BIST feature also
contains a Link Error Count and a Lock Status. If the connection of the serial link is broken, then the link error count is shown in
the register. When the PLL of the deserializer is locked or unlocked, the lock status can be read in the register. See Table 9.
Sample BIST Sequence
See Figure 17 for the BIST mode flow diagram.
Step 1:For the DS90UH925Q and DS90UH926Q FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin of DS90UH926Q
FPD-Link III deserializer. The desired clock source is selected through BISTC pin.
Step 2:The DS90UH925Q serializer is woken up through the back channel if it is not already on. The all zero pattern on the data
pins is sent through the FPD-Link III to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer
acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1
to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
Step 3:To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test
result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected,
the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The
BIST duration is user controlled by the duration of the BISTEN signal.
Step 4:The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 18 shows the waveform diagram of a
typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to
generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly
extending the cable length, faulting the interconnect, reducing signal condition enhancements ( Rx Equalization).
30136443
FIGURE 17. BIST Mode Flow Diagram
Forward Channel and Back Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal test pattern. The internal all-
zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to the deserializer. The deserializer on
locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and
dynamically indicates the status on PASS pin.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as indicated by link
detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The register is cleared when the serializer
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