DS90UH926Q Datasheet, PDF (18/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
OSCILLATOR OUTPUT
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is based on an internal
oscillator. The frequency of the oscillator may be selected. This feature is controlled by register Address 0x02, bit 5 (OSC Clock
Enable). See Table 9.
PIXEL CLOCK EDGE SELECT (RFB)
The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the Rising edge of the
PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for inter-operability with downstream devices.
The deserializer output does not need to use the same edge as the Ser input. This feature may be controlled by register. See
Table 9.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) AND OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW (depending on the
value of the OEN setting). After the DS90UH926Q completes its lock sequence to the input serial data, the LOCK output is driven
HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and PCLK outputs. The State
of the outputs are based on the OEN and OSS_SEL setting (Table 3) or register bit (Table 9). See Figure 7.
TABLE 3. Output States
Inputs
Serial
input
X
X
X
Static
Static
Active
Active
PDB OEN
0
X
1
0
1
0
1
1
1
1
1
1
1
1
Outputs
OSS_SE Lock
L
X
Z
0
L or H
1
L or H
0
L
1
L
0
H
1
H
Pass
Data, GPIO, I2S
Z
Z
L
L
Z
Z
L
L
Previous Status
L
Valid
L
L
Valid
CLK
Z
L
Z
L/OSC (Register bit
enable)
L
L
Valid
LOW FREQUENCY OPTIMIZATION (LFMODE)
The LFMODE is set via register (Table 9) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency of the deserializer.
If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High, the PCLK frequency is
between 5 MHz and <15 MHz. Please note when the device LFMODE is changed, a PDB reset is required.
INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)
1. On DS90UH925, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UH926Q deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UH925Q serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .
5. A read to HDCP_ISR will clear the interrupt at the DS90UH925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt source and clear the
interrupt driving INTB_IN. This would be when the downstream device releases the INTB_IN (pin 16) on the DS90UH926Q.
The system is now ready to return to step (1) at next falling edge of INTB_IN.
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