DS90UH926Q Datasheet, PDF (4/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
Pin Name
Pin #
I/O, Type Description
Control
PDB
59
I, LVCMOS Power-down Mode Input Pin
w/ pull-down PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized. .
OEN
31
Input, Output Enable Pin.
LVCMOS w/ See Table 3
pull-down
OSS_SEL
46
Input, Output Sleep State Select Pin.
LVCMOS w/ See Table 3
pull-down
MODE_SEL
15
I, Analog Device Configuration Select. See Table 4
BISTEN
44
I, LVCMOS BIST Enable Pin.
w/ pull-down 0: BIST Mode is disabled.
1: BIST Mode is enabled.
BISTC
16
I, LVCMOS BIST Clock Select.
w/ pull-down Shared with INTB_IN
0: PCLK; 1: 33 MHz
I2C
IDx
56
I, Analog I2C Serial Control Bus Device ID Address Select
External pull-up to V_DD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider.
See Figure 19
SCL
3
I/O,
I2C Clock Input / Output Interface
LVCMOS Must have an external pull-up to V_DD33, DO NOT FLOAT.
Open Drain _{Recommended pull-up: 4.7kΩ.}
SDA
2
I/O,
I2C Data Input / Output Interface
LVCMOS Must have an external pull-up to V_DD33, DO NOT FLOAT.
Open Drain _{Recommended pull-up: 4.7kΩ.}
Status
LOCK
32
O, LVCMOS LOCK Status Output Pin
w/ pull down 0: PLL is unlocked, RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled
by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS
42
O, LVCMOS PASS Output Pin
w/ pull down 0: One or more errors were detected in the received payload
1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
FPD-Link III Serial Interface
RIN+
49
I, LVDS True Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
RIN-
50
I, LVDS Inverting Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
CMLOUTP
52
O, LVDS True CML Output
Monitor point for equalized differential signal
CMLOUTN
53
O, LVDS Inverting CML Output
Monitor point for equalized differential signal
CMF
51
Analog Common Mode Filter. Connect 0.1 μF capacitor to GND
4
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