DS90UH926Q Datasheet, PDF (31/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
ADD
(dec)
3
ADD Register
(hex) Name
Bit(s)
0x03 Configuration 7
[1]
6
5
4
3
2
1
0
4 0x04 BCC
7:1
Watchdog
Control
0
5 0x05 I2C Control
7
[1]
6:4
3:0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default Function Descriptions
(hex)
0xF0
Reserved.
CRC
Generator
Enable
CRC Generator Enable (Back Channel)
1: Enable
0: Disable
Reserved
Filter
Enable
HS, VS, DE two clock filter When enabled, pulses less
than two full PCLK cycles on the DE, HS, and VS inputs
will be rejected
1: Filtering enable
0: Filtering disable
I2C Pass-
through
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
Auto ACK
ACK Select
1: Auto ACK enable
0: Self ACK
Reserved
RRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
0xFE
BCC
Watchdog
Timer
The watchdog timer allows termination of a control
channel transaction, if it fails to complete within a
programmed amount of time. This field sets the
Bidirectional Control Channel Watchdog Timeout value
in units of 2 milliseconds.
This field should not be set to 0
BCC
Watchdog
Timer
Disable
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation"
0x2E I2C Pass I2C Pass-Through All Transactions
Through All 1: Enabled
0: Disabled
I2C SDA
Hold Time
Internal I2C SDA Hold Time
It configures the amount of internal hold time provided
for the SDA input relative to the SCL input. Units are 50
ns.
I2C Filter
Depth
I2C Glitch Filter Depth
It configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5
ns.
Copyright © 1999-2012, Texas Instruments Incorporated
31