DS90UH926Q Datasheet, PDF (30/57 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
ADD
(dec)
2
ADD Register
(hex) Name
Bit(s)
0x02 Configuration 7
[0]
6
5
4
3
2
1
0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default Function Descriptions
(hex)
0x00 Output
Enable
LVCMOS Output Enable.
1: Enable
0: Disable. Tri-state Outputs
OEN and
OSS_SEL
Override
Overrides Output Enable Pin and Output State pin
1: Enable override
0: Disable - no override
OSC Clock
Enable
OSC Clock Output Enable
If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
Output
OSS Select to Control Output State during Lock Low
Sleep State Period
Select
1: Enable
(OSS_SEL) 0: Disable
Backward Backward Compatible (BC) mode set by MODE_SEL
Compatible pin or register.
select by 1: BC is set by register bit. Use register bit
pin or
reg_0x02[2] to set BC Mode
register 0: Use MODE_SEL pin.
control
Backward Backward compatible (BC) mode to DS90UR905Q or
Compatible DS90UR907Q, if reg_0x02[3] = 1
Mode
1: Backward compatible with DS90UR905Q or
Select
DS90UR907Q
(Set LFMODE = 0)
0: Backward Compatible is OFF (default)
LFMODE
select by
pin or
register
control
Frequency range is set by MODE_SEL pin or register
1: Frequency range is set by register. Use register
bitreg_0x02[0] to set LFMODE
0: Frequency range is set by MODE_SEL pin.
LFMODE
Frequency range select
1: PCLK range = 5 - <15 MHz, if reg_0x02[1] = 1
0: PCLK range = 15 - 85 MHz (default)
30
Copyright © 1999-2012, Texas Instruments Incorporated